Add the Device Tree binding documentation for the Microsemi Serval interrupt controller that is part of the ICPU. It is connected directly to the MIPS core interrupt controller. Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx> --- .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt index 94dc95cb815c..42de86e023a6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt @@ -1,10 +1,11 @@ Microsemi Ocelot SoC ICPU Interrupt Controller -Luton belongs the same family of Ocelot: the VCoreIII family +Luton and Servals belong the same family as Ocelot: the VCoreIII family Required properties: - compatible : should be "mscc,ocelot-icpu-intr" or "mscc,luton-icpu-intr" + or "mscc,serval-icpu-intr" - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an -- 2.28.0
