On 2020-10-28 10:11, Rafał Miłecki wrote:
[...]
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "brcm,cortex-b53", "arm,cortex-a53";
Erm, there's no binding for that - did you mean "brcm,brahma-b53"?
+ reg = <0x0>;
+ next-level-cache = <&l2>;
+ };
[...]
+ gic: interrupt-controller@81000000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
There's really no logical reason for a 64-bit system to pretend to be
compatible with Cortex-A9. This is presumably GIC-400 (or maybe GIC-500)
so it would be better to describe it as what it is.
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x00 0x81001000 0x00 0x1000>, <0x00 0x81002000 0x00 0x2000>;
+ };
[...]
+ pmu {
+ compatible = "arm,armv8-pmuv3";
Use the appropriate compatible for the actual CPUs - this is real
hardware, not a software model.
Robin.
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
