On 04.11.2020 04:33, Florian Fainelli wrote:
On 10/28/2020 3:11 AM, Rafał Miłecki wrote:
From: Rafał Miłecki <rafal@xxxxxxxxxx>
They don't descibe hardware fully yet but it's enough to boot a system.
Some missing blocks:
1. PMC (Power Management Controller?)
2. Crypto
3. Thermal
Asus misses defining full NAND partitions layout and buttons.
Further changes will fill those gaps as soon as required bindings will
be found / tested / added.
Signed-off-by: Rafał Miłecki <rafal@xxxxxxxxxx>
---
[snip]
+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "earlycon=bcm63xx_uart,0xff800640";
These bootargs should be dropped from the
Can you explain why, is that some kernel rule I missed? That's extremely helpful for debugging.
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "brcm,cortex-b53", "arm,cortex-a53";
Please drop "arm,cortex-a53"
+ reg = <0x0>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "brcm,cortex-b53", "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
The device that you have access to did not even ship with a version of PSCI?
Whenever trying to use psci defined as:
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
(with updated enable-method) I get:
psci: probing for conduit method from DT.
------------[ cut here ]------------
kernel BUG at arch/arm64/kernel/traps.c:406!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
CPU: 0 PID: 0 Comm: swapper Not tainted 5.10.0-rc2 #3
Hardware name: Asus GT-AC5300 (DT)
pstate: 00000085 (nzcv daIf -PAN -UAO -TCO BTYPE=--)
pc : do_undefinstr+0x2d8/0x300
lr : do_undefinstr+0x2e4/0x300
sp : ffffffc010933c60
x29: ffffffc010933c60 x28: ffffffc01093b680
x27: ffffffc0107a4c40 x26: ffffffc0107bcca0
x25: ffffffc010953c28 x24: 0000000000000080
x23: 0000000080000085 x22: ffffffc01099e100
x21: 00000000d4000003 x20: ffffffc01093b680
x19: ffffffc010933cd0 x18: ffffffc010942fd0
x17: 0000000000001400 x16: 0000000000001c00
x15: fffffffeffe00000 x14: ffffffffffffffff
x13: 0000000000000038 x12: 0101010101010101
x11: 0000000000000004 x10: 0101010101010101
x9 : 0000000000000004 x8 : 0000000000000004
x7 : 0000000000000000 x6 : ffffffc010933cb8
x5 : ffffffc010933cb8 x4 : ffffffc01093cf58
x3 : 0000000000000001 x2 : 0000000000000000
x1 : ffffffc01093b680 x0 : 0000000080000085
Call trace:
do_undefinstr+0x2d8/0x300
el1_sync_handler+0xbc/0x140
el1_sync+0x80/0x100
__arm_smccc_smc+0x0/0x2c
psci_probe+0x34/0x2c4
psci_0_2_init+0x18/0x24
psci_dt_init+0x64/0x8c
setup_arch+0x428/0x5c4
start_kernel+0x78/0x52c
Code: 17ffffa7 f9401bf7 17ffff80 f9001bf7 (d4210000)
random: get_random_bytes called from print_oops_end_marker+0x2c/0x70 with crng_init=0
---[ end trace 0000000000000000 ]---
Kernel panic - not syncing: Attempted to kill the idle task!
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "brcm,cortex-b53", "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "brcm,cortex-b53", "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ gic: interrupt-controller@81000000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
You would want to create a node that encapsulates the ARM peripheral
addresses within the SoC's physical address range, see
arch/arm/boot/dts/bcm63138.dtsi for an example with the axi bus node.
[snip]
+
+ nandcs: nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+ brcm,nand-has-wp;
Those last two properties should be moved to the board level DTS file.
+ };
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&timer>;
+ offset = <0x34>;
+ mask = <1>;
+ };
+ };
+};
