On 2020-10-30 14:08, Tomi Valkeinen wrote:
On 29/10/2020 16:52, Nishanth Menon wrote:
On 20:11-20201029, Nikhil Devshatwar wrote:
On 16:11-20201029, Tomi Valkeinen wrote:
DSS is IO coherent on AM65, so we can mark it as such with
'dma-coherent' property in the DT file.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@xxxxxx>
Acked-by: Nikhil Devshatwar <nikhil.nd@xxxxxx>
Tomi: Do you need to add Fixes: tag to percolate this to stable? if
yes, please comment, makes it easier for me to queue for 5.10 if
possible
I don't see this as a fix, but an optimization. Nothing is broken without this.
Note that if the driver doesn't have explicit control over what type of
memory access the device makes, that's not necessarily true.
If coherent DMA buffers are allocated from regular kernel memory,
there's still a cacheable alias kicking around that can be speculatively
fetched into a cache somewhere. If the device is genuinely non-coherent,
or configured to make non-snooping accesses, then that's not an issue,
but it it's hard-wired to make snooping accesses it can start hitting
that cached alias and not see subsequent updates to the buffer, since
those are written straight to RAM via the non-cacheable mapping. At that
point it becomes an actual problem (and it's not just theoretical -
we've hit a real-world example of this recently with GPUs on certain
Amlogic devices).
Robin.
