From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> Simple binding with a good description of why the spi-max-frequency is, in practice not as high as the datasheet implies. I've set the maximum as per the value established in the description. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> Cc: Matheus Tavares <matheus.bernardino@xxxxxx> Cc: Alexandru Ardelean <alexandru.ardelean@xxxxxxxxxx> --- .../bindings/iio/resolver/ad2s90.txt | 31 ---------- .../bindings/iio/resolver/adi,ad2s90.yaml | 60 +++++++++++++++++++ 2 files changed, 60 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/resolver/ad2s90.txt b/Documentation/devicetree/bindings/iio/resolver/ad2s90.txt deleted file mode 100644 index 477d41fa6467..000000000000 --- a/Documentation/devicetree/bindings/iio/resolver/ad2s90.txt +++ /dev/null @@ -1,31 +0,0 @@ -Analog Devices AD2S90 Resolver-to-Digital Converter - -https://www.analog.com/en/products/ad2s90.html - -Required properties: - - compatible: should be "adi,ad2s90" - - reg: SPI chip select number for the device - - spi-max-frequency: set maximum clock frequency, must be 830000 - - spi-cpol and spi-cpha: - Either SPI mode (0,0) or (1,1) must be used, so specify none or both of - spi-cpha, spi-cpol. - -See for more details: - Documentation/devicetree/bindings/spi/spi-bus.txt - -Note about max frequency: - Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns - delay is expected between the application of a logic LO to CS and the - application of SCLK, as also specified. And since the delay is not - implemented in the spi code, to satisfy it, SCLK's period should be at most - 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives - roughly 830000Hz. - -Example: -resolver@0 { - compatible = "adi,ad2s90"; - reg = <0>; - spi-max-frequency = <830000>; - spi-cpol; - spi-cpha; -}; diff --git a/Documentation/devicetree/bindings/iio/resolver/adi,ad2s90.yaml b/Documentation/devicetree/bindings/iio/resolver/adi,ad2s90.yaml new file mode 100644 index 000000000000..81e4bdfc17c4 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/resolver/adi,ad2s90.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD2S90 Resolver-to-Digital Converter + +maintainers: + - Matheus Tavares <matheus.bernardino@xxxxxx> + +description: | + Datasheet: https://www.analog.com/en/products/ad2s90.html + +properties: + compatible: + const: adi,ad2s90 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 830000 + description: | + Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns + delay is expected between the application of a logic LO to CS and the + application of SCLK, as also specified. And since the delay is not + implemented in the spi code, to satisfy it, SCLK's period should be at + most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives + roughly 830000Hz. + + spi-cpol: true + + spi-cpha: true + +additionalProperties: false + +required: + - compatible + - reg + +dependencies: + spi-cpol: [ spi-cpha ] + spi-cpha: [ spi-cpol ] + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + resolver@0 { + compatible = "adi,ad2s90"; + reg = <0>; + spi-max-frequency = <830000>; + spi-cpol; + spi-cpha; + }; + }; +... -- 2.28.0
