Hi Tero, On Thursday 19 June 2014 04:46 PM, Tero Kristo wrote: > On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote: >> Added missing 32khz clock used by PCIe PHY. >> The documention for this node can be found @ ../bindings/clock/ti/gate.txt. > > You can drop the node documentation ref, and rather add a TRM reference about > hardware details. Other than that, looks good to me. You mean something like why 32KHz clock is used (**PRCM.PCIE_32K_GFCLK (based on PRM.SYS_32K) for debounce and wakeup logic inside the PCIe1_PHY_RX**)? Or something like **Figure 26-19. PCIe PHY Subsystem Integration of DRA TRM vE shows how 32KHz clock is being used** ? Thanks Kishon > > -Tero > >> >> Cc: Tony Lindgren <tony@xxxxxxxxxxx> >> Cc: Rajendra Nayak <rnayak@xxxxxx> >> Cc: Tero Kristo <t-kristo@xxxxxx> >> Cc: Paul Walmsley <paul@xxxxxxxxx> >> Cc: Tony Lindgren <tony@xxxxxxxxxxx> >> Cc: Rob Herring <robh+dt@xxxxxxxxxx> >> Cc: Pawel Moll <pawel.moll@xxxxxxx> >> Cc: Mark Rutland <mark.rutland@xxxxxxx> >> Cc: Kumar Gala <galak@xxxxxxxxxxxxxx> >> Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx> >> --- >> arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> index 44993ec..e1bd052 100644 >> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> @@ -1165,6 +1165,14 @@ >> reg = <0x021c>, <0x0220>; >> }; >> >> + optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { >> + compatible = "ti,gate-clock"; >> + clocks = <&sys_32k_ck>; >> + #clock-cells = <0>; >> + reg = <0x13b0>; >> + ti,bit-shift = <8>; >> + }; >> + >> optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { >> compatible = "ti,divider-clock"; >> clocks = <&apll_pcie_ck>; >> > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html