The CPUfreq HW present in some Mediatek chipsets offloads the steps necessary for changing the frequency of CPUs. The driver implements the cpufreq driver interface for this hardware engine. This patch depends on MT6779 DTS patch[1] submitted by Hanks Chen. >From v7 to v8, there are three more patches based on patchset[2]. This patchset is about to register power table to Energy model for EAS and thermal usage. 1. EM CPU power table - Register energy model table for EAS and thermal cooling device usage. - Read the coresponding LUT for power table. 2. SVS initialization - The SVS(Smart Voltage Scaling) engine is a hardware which is used to calculate optimized voltage values for CPU power domain. DVFS driver could apply those optimized voltage values to reduce power consumption. - Driver will polling if HW engine is done for SVS initialization. After that, driver will read power table and register it to EAS. - CPUs must be in power on state when doing SVS. Use pm_qos to block cpu-idle state for SVS initializing. 3. Cooling device flag - Add cooling device flag for thermal [1] https://lkml.org/lkml/2020/8/4/1094 [2] https://lkml.org/lkml/2020/9/23/384 Hector.Yuan (3): cpufreq: mediatek-hw: Add support for CPUFREQ HW dt-bindings: arm: cpus: Document 'mediatek,freq-domain' property dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW Documentation/devicetree/bindings/arm/cpus.yaml | 6 + .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 113 +++++++ drivers/cpufreq/Kconfig.arm | 12 + drivers/cpufreq/Makefile | 1 + drivers/cpufreq/mediatek-cpufreq-hw.c | 343 ++++++++++++++++++++ 5 files changed, 475 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml create mode 100644 drivers/cpufreq/mediatek-cpufreq-hw.c
