There are some less-documented registers which control clocks and resets for the multimedia block which controls the LCDIF, ISI, MIPI CSI, and MIPI DSI. The i.Mx8M Nano appears to have a subset of the i.MX8MP registers with a couple shared registers with the i.MX8MM. This series builds on the series that have been submitted for both of those other two platforms. This is an RFC because when enabling the corresponding DTS node, the system freezes on power on. There are a couple of clocks that don't correspond to either the imx8mp nor the imx8mm, so I might have something wrong, and I was hoping for some constructive feedback in order to get the imx8m Nano to a similar point of the Mini and Plus. Adam Ford (3): dt-bindings: clock: imx8mn: Add media blk_ctl clock IDs dt-bindings: reset: imx8mn: Add media blk_ctl reset IDs clk: imx: Add blk-ctl driver for i.MX8MN drivers/clk/imx/clk-blk-ctl-imx8mn.c | 80 ++++++++++++++++++++++++ include/dt-bindings/clock/imx8mn-clock.h | 11 ++++ include/dt-bindings/reset/imx8mn-reset.h | 22 +++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/clk/imx/clk-blk-ctl-imx8mn.c create mode 100644 include/dt-bindings/reset/imx8mn-reset.h -- 2.25.1
