Supply top level nodes for the STiH416 based development boards.
The Pinctrl configuration has already been applied, so the only
missing piece of the DT puzzle is for a board's DTB to enable
the nodes.
Signed-off-by: Lee Jones <lee.jones@xxxxxxxxxx>
---
arch/arm/boot/dts/stih416.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 06473c5..8af159e 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -236,5 +236,45 @@
resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
<&softreset STIH416_KEYSCAN_SOFTRESET>;
};
+
+ /* SAS PWM Module */
+ pwm0: pwm@fed10000 {
+ compatible = "st,sti-pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ reg = <0xfed10000 0x68>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_chan0_default
+ &pinctrl_pwm0_chan1_default
+ &pinctrl_pwm0_chan2_default
+ &pinctrl_pwm0_chan3_default>;
+
+ clock-names = "pwm";
+ clocks = <&clk_sysin>;
+ };
+
+ /* SBC PWM Module */
+ pwm1: pwm@fe510000 {
+ compatible = "st,sti-pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ reg = <0xfe510000 0x68>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1_chan0_default
+ /*
+ * Shared with SBC_OBS_NOTRST. Don't
+ * enable unless you really know what
+ * you're doing.
+ *
+ * &pinctrl_pwm1_chan1_default
+ */
+ &pinctrl_pwm1_chan2_default
+ &pinctrl_pwm1_chan3_default>;
+
+ clock-names = "pwm";
+ clocks = <&clk_sysin>;
+ };
};
};
--
1.8.3.2
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