This change will add support to read QPIC version.
QPIC version V2.0 onwards some new register introduced
in QPIC. So based on hw_version we will update those
register.
Signed-off-by: Md Sadre Alam <mdalam@xxxxxxxxxxxxxx>
---
drivers/mtd/nand/raw/qcom_nandc.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index f5064ab..eabb803 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -443,6 +443,7 @@ struct qcom_nand_controller {
u32 cmd1, vld;
const struct qcom_nandc_props *props;
+ u32 hw_version;
};
/*
@@ -2538,6 +2539,7 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
int ecc_mode = 1;
int num_addr_cycle = 5, dsbl_sts_aftr_write = 0;
int wr_rd_bsy_gap = 2, recovery_cycle = 7;
+ u32 version_reg;
/* controller only supports 512 bytes data steps */
ecc->size = NANDC_STEP_SIZE;
@@ -2545,6 +2547,26 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
cwperpage = mtd->writesize / NANDC_STEP_SIZE;
/*
+ * Read the required ecc strength from NAND device and overwrite the
+ * device tree ecc strength
+ */
+ if (chip->base.eccreq.strength >= 8)
+ ecc->strength = 8;
+
+ /* Read QPIC version register */
+ if (nandc->props->is_serial_nand)
+ version_reg = (NAND_VERSION + 0x4000);
+ else
+ version_reg = NAND_VERSION;
+ nandc->hw_version = nandc_read(nandc, version_reg);
+ pr_debug("QPIC controller hw version Major:%d, Minor:%d\n",
+ ((nandc->hw_version & NAND_VERSION_MAJOR_MASK)
+ >> NAND_VERSION_MAJOR_SHIFT),
+ ((nandc->hw_version & NAND_VERSION_MINOR_MASK)
+ >> NAND_VERSION_MINOR_SHIFT));
+ nandc->hw_version = ((nandc->hw_version & NAND_VERSION_MAJOR_MASK)
+ >> NAND_VERSION_MAJOR_SHIFT);
+ /*
* Each CW has 4 available OOB bytes which will be protected with ECC
* so remaining bytes can be used for ECC.
*/
--
2.7.4
