> -----Original Message----- > From: Marek Vasut [mailto:marex@xxxxxxx] > Sent: Friday, October 9, 2020 3:27 PM > To: Jacky Bai <ping.bai@xxxxxxx>; Lucas Stach <l.stach@xxxxxxxxxxxxxx>; > Shawn Guo <shawnguo@xxxxxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx> > Cc: devicetree@xxxxxxxxxxxxxxx; Frieder Schrempf > <frieder.schrempf@xxxxxxxxxx>; patchwork-lst@xxxxxxxxxxxxxx; dl-linux-imx > <linux-imx@xxxxxxx>; kernel@xxxxxxxxxxxxxx; Fabio Estevam > <festevam@xxxxxxxxx>; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > Subject: Re: [PATCH 04/11] soc: imx: gpcv2: wait for ADB400 handshake > > On 10/9/20 5:05 AM, Jacky Bai wrote: > [...] > > >>>>> @@ -176,9 +180,19 @@ static int imx_pgc_power_up(struct > >> generic_pm_domain *genpd) > >>>>> GPC_PGC_CTRL_PCR, 0); > >>>>> > >>>>> /* request the ADB400 to power up */ > >>>>> - if (domain->bits.hsk) > >>>>> + if (domain->bits.hskreq) { > >>>>> regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, > >>>>> - domain->bits.hsk, domain->bits.hsk); > >>>>> + domain->bits.hskreq, domain->bits.hskreq); > >>>>> + > >>>>> + ret = regmap_read_poll_timeout(domain->regmap, > >> GPC_PU_PWRHSK, > >>>>> + reg_val, > >>>>> + (reg_val & domain->bits.hskack), > >>>>> + 0, USEC_PER_MSEC); > >>>>> + if (ret) { > >>>>> + dev_err(domain->dev, "failed to power up ADB400\n"); > >>>> > >>>> The ADB400 is a bus bridge, so the bus is being attached here, not > >>>> powered up, right ? > >>> > >>> The bits in the PWRHSK register are called "power down" bits, so I > >>> kept this nomenclature. Also I think the ADB400 is mostly isolating > >>> the bus in the power domains from the rest of the NoC, "attaching" > >>> of the bus is really disabling the isolation. > >>> > >>> As there are multiple valid naming choices I kept the naming from > >>> the RM. > >> > >> Maybe NXP can finally explain what these bits really do ? > > > > This bit is used to sync the ADB400 bridge to a known status before MIX side > power down & isolation. > > Detailed info can be find in ARM's ADB400 TRM. > > Is this documentation publicly available ? Ooh, Sorry, It seems confidential. Some info shared below: When the powerdown interface is used then the bridge must enter the idle state before either domain can be reset or powered down: 1. The ADB-400 must be quiescent before a powerdown request. It is a system responsibility to ensure that all transactions are completed and no new transactions are sent to ADB-400. 2. When the ADB-400 receives the powerdown request signal, pwrdnreqn, LOW it ensures that all FIFOs are empty, pointers are reset to zero, and no false transactions can be generated. 3. When the ADB-400 completes the internal shutdown process, it sets the pwrdnackn signal LOW. The interface is in idle state and powerdown can commence. BR Jacky Bai
