> -----Original Message----- > From: Rob Herring <robh@xxxxxxxxxx> > Sent: Tuesday, October 6, 2020 11:25 PM > To: Ardelean, Alexandru <alexandru.Ardelean@xxxxxxxxxx> > Cc: linux-clk@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; Hennerich, Michael > <Michael.Hennerich@xxxxxxxxxx>; lars@xxxxxxxxxx; sboyd@xxxxxxxxxx; > mturquette@xxxxxxxxxxxx; mdf@xxxxxxxxxx > Subject: Re: [PATCH] dt-bindings: clock: adi,axi-clkgen: convert old binding to > yaml format > > On Thu, Oct 01, 2020 at 11:50:35AM +0300, Alexandru Ardelean wrote: > > This change converts the old binding for the AXI clkgen driver to a > > yaml format. > > > > As maintainers, added: > > - Lars-Peter Clausen <lars@xxxxxxxxxx> - as original author of driver & > > binding > > Do you have permission for relicensing? The default was GPL-2.0. I talked to Michael Hennerich [he's cc-ed], and we have permission from his side. I think Lars would need to provide permission as well, as the author. If we won't have a reply from him [after by some time-frame] I'll leave it as GPL-2.0. I'm a bit clumsy about licensing in general; and I don't care about it all that much. > > > - Michael Hennerich <michael.hennerich@xxxxxxxxxx> - as supporter of > > Analog Devices drivers > > > > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@xxxxxxxxxx> > > --- > > .../bindings/clock/adi,axi-clkgen.yaml | 52 +++++++++++++++++++ > > .../devicetree/bindings/clock/axi-clkgen.txt | 25 --------- > > 2 files changed, 52 insertions(+), 25 deletions(-) create mode > > 100644 Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml > > delete mode 100644 > > Documentation/devicetree/bindings/clock/axi-clkgen.txt > > > > diff --git > > a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml > > b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml > > new file mode 100644 > > index 000000000000..45497f370cb3 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml > > @@ -0,0 +1,52 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > +https://urldefense.com/v3/__http://devicetree.org/schemas/clock/adi,a > > +xi- > clkgen.yaml*__;Iw!!A3Ni8CS0y2Y!s_aQs5F13Tud7X5wmDjgyOhkPGGpnQgdtN7 > > +apmY8mrX_fgQOlQvZTtRGBSIpmJtDghVa8A$ > > +$schema: > > +https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.y > > > +aml*__;Iw!!A3Ni8CS0y2Y!s_aQs5F13Tud7X5wmDjgyOhkPGGpnQgdtN7apmY8 > mrX_fg > > +QOlQvZTtRGBSIpmJuCLAwQnQ$ > > + > > +title: Binding for Analog Devices AXI clkgen pcore clock generator > > + > > +maintainers: > > + - Lars-Peter Clausen <lars@xxxxxxxxxx> > > + - Michael Hennerich <michael.hennerich@xxxxxxxxxx> > > + > > +description: | > > + The axi_clkgen IP core is a software programmable clock generator, > > + that can be synthesized on various FPGA platforms. > > + > > + Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen > > + > > +properties: > > + compatible: > > + enum: > > + - adi,axi-clkgen-2.00.a > > + > > + clocks: > > + description: > > + Phandle and clock specifier for the parent clock(s). > > Drop, that's every 'clocks'. > > > This must either > > + reference one clock if only the first clock input is connected or two > > + if both clock inputs are connected. For the later case the clock > > + connected to the first input must be specified first. > > That doesn't really say what the 2 clocks are. > > > + minItems: 1 > > + maxItems: 2 > > + > > + '#clock-cells': > > + const: 0 > > + > > + reg: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - '#clock-cells' > > additionalProperties: false > > > + > > +examples: > > + - | > > + clock@ff000000 { > > clock-controller@... > > > + compatible = "adi,axi-clkgen-2.00.a"; > > + #clock-cells = <0>; > > + reg = <0xff000000 0x1000>; > > + clocks = <&osc 1>; > > + }; > > diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt > > b/Documentation/devicetree/bindings/clock/axi-clkgen.txt > > deleted file mode 100644 > > index aca94fe9416f..000000000000 > > --- a/Documentation/devicetree/bindings/clock/axi-clkgen.txt > > +++ /dev/null > > @@ -1,25 +0,0 @@ > > -Binding for the axi-clkgen clock generator > > - > > -This binding uses the common clock binding[1]. > > - > > -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt > > - > > -Required properties: > > -- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a". > > -- #clock-cells : from common clock binding; Should always be set to 0. > > -- reg : Address and length of the axi-clkgen register set. > > -- clocks : Phandle and clock specifier for the parent clock(s). This must > > - either reference one clock if only the first clock input is connected or > two > > - if both clock inputs are connected. For the later case the clock > connected > > - to the first input must be specified first. > > - > > -Optional properties: > > -- clock-output-names : From common clock binding. > > - > > -Example: > > - clock@ff000000 { > > - compatible = "adi,axi-clkgen"; > > - #clock-cells = <0>; > > - reg = <0xff000000 0x1000>; > > - clocks = <&osc 1>; > > - }; > > -- > > 2.17.1 > >
