On 9/30/20 5:50 PM, Lucas Stach wrote:
> Normally the reset for the devices inside the power domain is
> triggered automatically from the PGC in the power-up sequencing,
> however on i.MX8MM this doesn't work for the GPU power domains.
One has to wonder whether the VPU power domain has similar hardware bug
on the MX8MM ?
[...]
> @@ -112,6 +113,7 @@ struct imx_pgc_domain {
> struct regulator *regulator;
> struct clk *clk[GPC_CLK_MAX];
> int num_clks;
> + struct reset_control *reset;
Keep this sorted as reverse xmas tree please.
> unsigned int pgc;
[...]
