On Tue, 15 Sep 2020 15:03:37 +0200, Neil Armstrong wrote: > The PHY registers happens to be at the beginning of a large zone containing > interleaved system registers (mainly clocks, power management, PHY control..), > found in all Amlogic SoC so far. > > The goal is to model it the same way as the other "features" of this zone, > like Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt > and Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml > and have a coherent bindings scheme over the Amlogic SoCs. > > This update the description, removed the reg attribute then updates the example > accordingly. > > Signed-off-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx> > --- > .../phy/amlogic,meson-axg-mipi-pcie-analog.yaml | 17 +++++++++++------ > 1 file changed, 11 insertions(+), 6 deletions(-) > Acked-by: Rob Herring <robh@xxxxxxxxxx>
