Hi,
On Mon, Sep 21, 2020 at 11:43:02PM -0300, Matheus Castello wrote:
> Add Device Trees for Caninos Loucos Labrador CoM Core v3 and base board
> M v2. Based on the work of Andreas Färber on Cubieboard 7 device tree.
>
> Signed-off-by: Matheus Castello <matheus@xxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/actions/Makefile | 2 +
> .../dts/actions/s700-labrador-base-m2.dts | 34 +++++
> .../boot/dts/actions/s700-labrador-v3.dtsi | 122 ++++++++++++++++++
> 3 files changed, 158 insertions(+)
> create mode 100644 arch/arm64/boot/dts/actions/s700-labrador-base-m2.dts
> create mode 100644 arch/arm64/boot/dts/actions/s700-labrador-v3.dtsi
>
> diff --git a/arch/arm64/boot/dts/actions/Makefile b/arch/arm64/boot/dts/actions/Makefile
> index b57fd2372ecd..3765697fa91e 100644
> --- a/arch/arm64/boot/dts/actions/Makefile
> +++ b/arch/arm64/boot/dts/actions/Makefile
> @@ -2,4 +2,6 @@
>
> dtb-$(CONFIG_ARCH_ACTIONS) += s700-cubieboard7.dtb
>
> +dtb-$(CONFIG_ARCH_ACTIONS) += s700-labrador-base-m2.dtb
> +
> dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb
> diff --git a/arch/arm64/boot/dts/actions/s700-labrador-base-m2.dts b/arch/arm64/boot/dts/actions/s700-labrador-base-m2.dts
> new file mode 100644
> index 000000000000..63bbca46475b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/actions/s700-labrador-base-m2.dts
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Matheus Castello
> + */
> +
> +/dts-v1/;
> +
> +#include "s700-labrador-v3.dtsi"
> +
> +/ {
> + compatible = "caninos,labrador-base-m2",
> + "caninos,labrador-v3", "actions,s700";
> + model = "Caninos Labrador Core v3 on Labrador Base-M v2";
> +
> + aliases {
> + serial3 = &uart3;
> + };
> +
> + chosen {
> + stdout-path = "serial3:115200n8";
> + };
> +};
> +
> +&uart3 {
> + status = "okay";
No fixed clock?
> +};
> +
> +&i2c0 {
> + status = "okay";
> +};
> +
> +&i2c1 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/actions/s700-labrador-v3.dtsi b/arch/arm64/boot/dts/actions/s700-labrador-v3.dtsi
> new file mode 100644
> index 000000000000..91addba6382b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/actions/s700-labrador-v3.dtsi
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Matheus Castello
> + */
> +
> +#include "s700.dtsi"
> +
> +/ {
> + compatible = "caninos,labrador-v3", "actions,s700";
> + model = "Caninos Labrador Core v3.1";
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x80000000>;
> + };
> +
> + memory@1,e0000000 {
> + device_type = "memory";
> + reg = <0x1 0xe0000000 0x0 0x0>;
> + };
> +
What is the size of this memory? The datasheet says only 512MB Max.
> + /* Labrador v3 firmware does not support PSCI */
Oops. This is unfortunate... I'm not sure if this is even acceptable for
ARM64 machines.
Let me add Olof and Arnd...
Thanks,
Mani
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x1f000020>;
> + next-level-cache = <&L2>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x1f000020>;
> + next-level-cache = <&L2>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x1f000020>;
> + next-level-cache = <&L2>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x1f000020>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> + L2: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> +};
> +
> +&timer {
> + clocks = <&hosc>;
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_default>;
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_default>;
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_default>;
> +};
> +
> +&pinctrl {
> + i2c0_default: i2c0_default {
> + pinmux {
> + groups = "i2c0_mfp";
> + function = "i2c0";
> + };
> + pinconf {
> + pins = "i2c0_sclk", "i2c0_sdata";
> + bias-pull-up;
> + };
> + };
> +
> + i2c1_default: i2c1_default {
> + pinmux {
> + groups = "i2c1_dummy";
> + function = "i2c1";
> + };
> + pinconf {
> + pins = "i2c1_sclk", "i2c1_sdata";
> + bias-pull-up;
> + };
> + };
> +
> + i2c2_default: i2c2_default {
> + pinmux {
> + groups = "i2c2_dummy";
> + function = "i2c2";
> + };
> + pinconf {
> + pins = "i2c2_sclk", "i2c2_sdata";
> + bias-pull-up;
> + };
> + };
> +};
> --
> 2.28.0
>
