On Thu, Sep 10, 2020 at 12:27:18AM +0800, vijayakannan.ayyathurai@xxxxxxxxx wrote:
> From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@xxxxxxxxx>
>
> The Intel Keem Bay SoC requires PWM support.
> Add the pwm-keembay driver to enable this.
>
> Signed-off-by: Lai, Poey Seng <poey.seng.lai@xxxxxxxxx>
> Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@xxxxxxxxx>
> Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@xxxxxxxxx>
> Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@xxxxxxxxx>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> ---
> drivers/pwm/Kconfig | 9 ++
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-keembay.c | 232 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 242 insertions(+)
> create mode 100644 drivers/pwm/pwm-keembay.c
>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 7dbcf6973d33..4f1fdbc2e5e3 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -254,6 +254,15 @@ config PWM_JZ4740
> To compile this driver as a module, choose M here: the module
> will be called pwm-jz4740.
>
> +config PWM_KEEMBAY
> + tristate "Intel Keem Bay PWM driver"
> + depends on ARM64 || COMPILE_TEST
> + help
> + The platform driver for Intel Keem Bay PWM controller.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-keembay.
I wonder about the dependency. If this is an external chip it should be
possible to be used on platforms other than ARM64. If this is only part
of a certain SoC: Isn't there a more specific symbol than ARM64 to
depend on?
> +
> config PWM_LP3943
> tristate "TI/National Semiconductor LP3943 PWM support"
> depends on MFD_LP3943
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index 2c2ba0a03557..a1051122eb07 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o
> obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o
> obj-$(CONFIG_PWM_IQS620A) += pwm-iqs620a.o
> obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
> +obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o
> obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o
> obj-$(CONFIG_PWM_LPC18XX_SCT) += pwm-lpc18xx-sct.o
> obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o
> diff --git a/drivers/pwm/pwm-keembay.c b/drivers/pwm/pwm-keembay.c
> new file mode 100644
> index 000000000000..6f41b1c0ae9a
> --- /dev/null
> +++ b/drivers/pwm/pwm-keembay.c
> @@ -0,0 +1,232 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Intel Keem Bay PWM driver
> + *
> + * Copyright (C) 2020 Intel Corporation
> + * Authors: Lai Poey Seng <poey.seng.lai@xxxxxxxxx>
> + * Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@xxxxxxxxx>
> + *
> + * Limitations:
> + * - Upon disabling a channel, the currently running
> + * period will not be completed. However, upon
> + * reconfiguration of the duty cycle/period, the
> + * currently running period will be completed first.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
> +#include <linux/regmap.h>
> +
> +#define KMB_TOTAL_PWM_CHANNELS 6
> +#define KMB_PWM_COUNT_MAX 0xffff
> +#define KMB_PWM_EN_BIT BIT(31)
> +
> +/* Mask */
> +#define KMB_PWM_HIGH_MASK GENMASK(31, 16)
> +#define KMB_PWM_LOW_MASK GENMASK(15, 0)
> +#define KMB_PWM_LEADIN_MASK GENMASK(30, 0)
> +
> +/* PWM Register offset */
> +#define KMB_PWM_LEADIN_OFFSET(ch) (0x00 + 4 * (ch))
> +#define KMB_PWM_HIGHLOW_OFFSET(ch) (0x20 + 4 * (ch))
> +
> +struct keembay_pwm {
> + struct pwm_chip chip;
> + struct device *dev;
> + struct clk *clk;
> + void __iomem *base;
> +};
> +
> +static inline struct keembay_pwm *to_keembay_pwm_dev(struct pwm_chip *chip)
> +{
> + return container_of(chip, struct keembay_pwm, chip);
> +}
> +
> +static inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask,
> + u32 val, u32 offset)
> +{
> + u32 buff = readl(priv->base + offset);
> +
> + buff = u32_replace_bits(buff, val, mask);
> + writel(buff, priv->base + offset);
> +}
> +
> +static void keembay_pwm_enable(struct keembay_pwm *priv, int ch)
> +{
> + keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1,
> + KMB_PWM_LEADIN_OFFSET(ch));
> +}
> +
> +static void keembay_pwm_disable(struct keembay_pwm *priv, int ch)
> +{
> + keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0,
> + KMB_PWM_LEADIN_OFFSET(ch));
> +}
> +
> +static void keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
> + struct pwm_state *state)
> +{
> + struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
> + unsigned long long pwm_h_count, pwm_l_count;
> + unsigned long clk_rate;
> + u32 buff;
> +
> + clk_rate = clk_get_rate(priv->clk);
> +
> + /* Read channel enabled status */
> + buff = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
> + if (buff & KMB_PWM_EN_BIT)
> + state->enabled = true;
> + else
> + state->enabled = false;
> +
> + /* Read period and duty cycle */
> + buff = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
> + pwm_l_count = FIELD_GET(KMB_PWM_LOW_MASK, buff) * NSEC_PER_SEC;
> + pwm_h_count = FIELD_GET(KMB_PWM_HIGH_MASK, buff) * NSEC_PER_SEC;
> + state->duty_cycle = DIV_ROUND_UP_ULL(pwm_h_count, clk_rate);
> + state->period = DIV_ROUND_UP_ULL(pwm_h_count + pwm_l_count, clk_rate);
> +}
> +
> +static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> + const struct pwm_state *state)
> +{
> + struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
> + struct pwm_state current_state;
> + u16 pwm_h_count, pwm_l_count;
> + unsigned long long div;
> + unsigned long clk_rate;
> + u32 pwm_count = 0;
> +
> + if (state->polarity != PWM_POLARITY_NORMAL)
> + return -ENOSYS;
> +
> + keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0,
> + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
> +
> + keembay_pwm_get_state(chip, pwm, ¤t_state);
> +
> + if (!state->enabled) {
> + if (current_state.enabled)
> + keembay_pwm_disable(priv, pwm->hwpwm);
> + return 0;
> + }
> +
> + /*
> + * The upper 16 bits of the KMB_PWM_HIGHLOW_OFFSET register contain
> + * the high time of the waveform, while the last 16 bits contain
> + * the low time of the waveform, in terms of clock cycles.
> + *
> + * high time = clock rate * duty cycle
> + * low time = clock rate * (period - duty cycle)
> + *
> + * e.g. For period 50us, duty cycle 30us, and clock rate 500MHz:
> + * high time = 500MHz * 30us = 0x3A98
> + * low time = 500MHz * 20us = 0x2710
> + * Value written to KMB_PWM_HIGHLOW_OFFSET = 0x3A982710
> + */
> +
> + clk_rate = clk_get_rate(priv->clk);
> +
> + /* Configure waveform high time */
> + div = clk_rate * state->duty_cycle;
> + div = DIV_ROUND_CLOSEST_ULL(div, NSEC_PER_SEC);
Please round down here.
> + if (div > KMB_PWM_COUNT_MAX)
> + return -ERANGE;
> +
> + pwm_h_count = div;
> +
> + /* Configure waveform low time */
> + div = clk_rate * (state->period - state->duty_cycle);
> + div = DIV_ROUND_CLOSEST_ULL(div, NSEC_PER_SEC);
> + if (div > KMB_PWM_COUNT_MAX)
> + return -ERANGE;
> +
> + pwm_l_count = div;
This isn't right, too.
I think the right formula is:
div = (clk_rate * state->period) / NSEC_PER_SEC - pwm_h_count
Consider:
clk_rate = 333334 [Hz]
state.duty_cycle = 1000500 [ns]
state.period = 2001000 [ns]
With your calculation (and rounding down in the divisions calculation)
this results in
pwm_h_count = 333
pwm_l_count = 333
and so a period length of 666 clock ticks (1997996 ns) while it should be
667 clock ticks (2000995 ns).
> +
> + pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, pwm_h_count) |
> + FIELD_PREP(KMB_PWM_LOW_MASK, pwm_l_count);
> +
> + writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
> +
> + if (state->enabled && !current_state.enabled)
> + keembay_pwm_enable(priv, pwm->hwpwm);
> +
> + return 0;
> +}
> +
> +static const struct pwm_ops keembay_pwm_ops = {
> + .owner = THIS_MODULE,
> + .apply = keembay_pwm_apply,
> + .get_state = keembay_pwm_get_state,
> +};
> +
> +static int keembay_pwm_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct keembay_pwm *priv;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(priv->clk))
> + return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");
> +
> + ret = clk_prepare_enable(priv->clk);
> + if (ret)
> + return ret;
> +
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + priv->chip.base = -1;
> + priv->chip.dev = dev;
> + priv->chip.ops = &keembay_pwm_ops;
> + priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS;
> +
> + ret = pwmchip_add(&priv->chip);
> + if (ret) {
> + dev_err(dev, "Failed to add PWM chip: %pe\n", ERR_PTR(ret));
> + return ret;
> + }
> +
> + platform_set_drvdata(pdev, priv);
> +
> + return 0;
clk_disable_unprepare is missing in the two last error paths.
> +}
> +
> +static int keembay_pwm_remove(struct platform_device *pdev)
> +{
> + struct keembay_pwm *priv = platform_get_drvdata(pdev);
> +
> + return pwmchip_remove(&priv->chip);
clk_disable_unprepare is missing here, too.
> +}
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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