On Fri, Sep 18, 2020 at 12:24 PM Robin Murphy <robin.murphy@xxxxxxx> wrote: > > Document the requirements for the CMN-600 DT binding. The internal > topology is almost entirely discoverable by walking a tree of ID > registers, but sadly both the starting point for that walk and the > exact format of those registers are configuration-dependent and not > discoverable from some sane fixed location. Oh well. > > Signed-off-by: Robin Murphy <robin.murphy@xxxxxxx> > --- > > fix up $id as well, oops... > > .../devicetree/bindings/perf/arm,cmn.yaml | 57 +++++++++++++++++++ > 1 file changed, 57 insertions(+) > create mode 100644 Documentation/devicetree/bindings/perf/arm,cmn.yaml Do you expect this to cover more than cmn-600? If not, use the compatible string for the file name. > > diff --git a/Documentation/devicetree/bindings/perf/arm,cmn.yaml b/Documentation/devicetree/bindings/perf/arm,cmn.yaml > new file mode 100644 > index 000000000000..e4fcc0de25e2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/arm,cmn.yaml > @@ -0,0 +1,57 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright 2020 Arm Ltd. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/perf/arm,cmn.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Arm CMN (Coherent Mesh Network) Performance Monitors > + > +maintainers: > + - Robin Murphy <robin.murphy@xxxxxxx> > + > +properties: > + compatible: > + const: arm,cmn-600 > + > + reg: > + items: > + - description: Physical address of the base (PERIPHBASE) and > + size (up to 64MB) of the configuration address space. > + > + interrupts: > + minItems: 1 > + maxItems: 4 > + items: > + - description: Overflow interrupt for DTC0 > + - description: Overflow interrupt for DTC1 > + - description: Overflow interrupt for DTC2 > + - description: Overflow interrupt for DTC3 > + description: One interrupt for each DTC domain implemented must > + be specified, in order. DTC0 is always present. What's DTC? > + > + arm,root-node: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Offset from PERIPHBASE of the configuration > + discovery node (see TRM definition of ROOTNODEBASE). You can enforce some alignment: multipleOf: 0x4000 > + > +required: > + - compatible > + - reg > + - interrupts > + - arm,root-node > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + pmu@50000000 { > + compatible = "arm,cmn-600"; > + reg = <0x50000000 0x4000000>; > + /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */ > + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; > + arm,root-node = <0x104000>; > + }; > +... > -- > 2.28.0.dirty
