On 8/24/2020 7:10 AM, Biju Das wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Convert ti,hd3ss3220.txt to YAML. Updated the binding documentation > as graph bindings of this device model Super Speed (SS) data bus to > the Super Speed (SS) capable connector. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > --- > v2->v3: Replaced Tabs with spaces in the example section. > v1->v2 : No change > Ref: https://patchwork.kernel.org/patch/11669423/ > --- > .../devicetree/bindings/usb/ti,hd3ss3220.txt | 38 --------- > .../devicetree/bindings/usb/ti,hd3ss3220.yaml | 81 +++++++++++++++++++ > 2 files changed, 81 insertions(+), 38 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt > create mode 100644 Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml > > diff --git a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt > deleted file mode 100644 > index 2bd21b22ce95..000000000000 > --- a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt > +++ /dev/null > @@ -1,38 +0,0 @@ > -TI HD3SS3220 TypeC DRP Port Controller. > - > -Required properties: > - - compatible: Must be "ti,hd3ss3220". > - - reg: I2C slave address, must be 0x47 or 0x67 based on ADDR pin. > - - interrupts: An interrupt specifier. > - > -Required sub-node: > - - connector: The "usb-c-connector" attached to the hd3ss3220 chip. The > - bindings of the connector node are specified in: > - > - Documentation/devicetree/bindings/connector/usb-connector.yaml > - > -Example: > -hd3ss3220@47 { > - compatible = "ti,hd3ss3220"; > - reg = <0x47>; > - interrupt-parent = <&gpio6>; > - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > - > - connector { > - compatible = "usb-c-connector"; > - label = "USB-C"; > - data-role = "dual"; > - > - ports { > - #address-cells = <1>; > - #size-cells = <0>; > - > - port@1 { > - reg = <1>; > - hd3ss3220_ep: endpoint { > - remote-endpoint = <&usb3_role_switch>; > - }; > - }; > - }; > - }; > -}; > diff --git a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml > new file mode 100644 > index 000000000000..750a099529c0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml > @@ -0,0 +1,81 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/ti,hd3ss3220.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: TI HD3SS3220 TypeC DRP Port Controller > + > +maintainers: > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > + > +description: |- > + HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel > + Configuration (CC) logic and 5V VCONN sourcing for ecosystems implementing USB Type-C. The > + HD3SS3220 can be configured as a Downstream Facing Port (DFP), Upstream Facing Port (UFP) or a > + Dual Role Port (DRP) making it ideal for any application. > + > +properties: > + compatible: > + const: ti,hd3ss3220 > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + ports: > + description: OF graph bindings (specified in bindings/graph.txt) that model > + SS data bus to the SS capable connector. > + type: object > + properties: > + port@0: > + type: object > + description: Super Speed (SS) capable connector. > + > + port@1: > + type: object > + description: Super Speed (SS) data bus. > + > + required: > + - port@0 > + - port@1 > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + i2c0 { > + #address-cells = <1>; > + #size-cells = <0>; > + > + hd3ss3220@47 { > + compatible = "ti,hd3ss3220"; > + reg = <0x47>; > + interrupt-parent = <&gpio6>; > + interrupts = <3>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + hd3ss3220_in_ep: endpoint { > + remote-endpoint = <&ss_ep>; > + }; Hi Biju, I'm involved in a separate thread[1] and I just wanted to get your inputs on how you understood the port and endpoint assignments for the USB type C connectors in different designs. Since the hd3ss3220 does the type C lane detect and has an integrated lane select mux, what is the ss_ep being used for? Thanks Wesley [1] https://lore.kernel.org/linux-usb/0101017458361303-16620b87-c433-4c00-a061-b1e688363539-000000@xxxxxxxxxxxxxxxxxxxxxxx/ > + }; > + port@1 { > + reg = <1>; > + hd3ss3220_out_ep: endpoint { > + remote-endpoint = <&usb3_role_switch>; > + }; > + }; > + }; > + }; > + }; > -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
