When WIZ wraps a Cadence Torrent PHY (instead of Cadence Sierra PHY)
there is a difference in the refclk-dig node: Torrent only has two
clocks instead of Sierra's four clocks. Add minItems: 2 to solve this.
Additionally, in our use case we only need to use assigned-clock for a
single clock, but the current binding requires either no assigned-clocks
or two. Fix this by adding minItems: 1 to all the assigned-clock
properties.
There was also an extra trailing whitespace, which this patch removes.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@xxxxxx>
---
.../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index 5ffc95c62909..c33e9bc79521 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -45,9 +45,15 @@ properties:
ranges: true
assigned-clocks:
+ minItems: 1
maxItems: 2
assigned-clock-parents:
+ minItems: 1
+ maxItems: 2
+
+ assigned-clock-rates:
+ minItems: 1
maxItems: 2
typec-dir-gpios:
@@ -119,9 +125,10 @@ patternProperties:
logic.
properties:
clocks:
+ minItems: 2
maxItems: 4
- description: Phandle to four clock nodes representing the inputs to
- refclk_dig
+ description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
+ the inputs to refclk_dig
"#clock-cells":
const: 0
@@ -203,7 +210,7 @@ examples:
};
refclk-dig {
- clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
<&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>;
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
