Hi,
On 10/09/2020 10:43, Hsin-Yi Wang wrote:
Set uart iotype to mmio32 to make earlycon work with stdout-path.
Signed-off-by: Hsin-Yi Wang <hsinyi@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 5e046f9d48ce9..ca6ea71f5f435 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -613,6 +613,8 @@ uart0: serial@11002000 {
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
clock-names = "baud", "bus";
+ reg-io-width = <4>;
Why do we need that, we have
device->port.iotype = UPIO_MEM32;
in early_mtk8250_setup(). That should do the job already.
+ reg-shift = <2>;
Can't we just add
device->port.regshift = 2;
to early_mtk8250_setup()? I think that would be a cleaner solution. As the
serial device is the same for all SoCs, I don't expect any regression here.
CCing Eddie to correct me, if I'm wrong :)
Regards,
Matthias
status = "disabled";
};
@@ -623,6 +625,8 @@ uart1: serial@11003000 {
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
clock-names = "baud", "bus";
+ reg-io-width = <4>;
+ reg-shift = <2>;
status = "disabled";
};
@@ -633,6 +637,8 @@ uart2: serial@11004000 {
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
clock-names = "baud", "bus";
+ reg-io-width = <4>;
+ reg-shift = <2>;
status = "disabled";
};
@@ -643,6 +649,8 @@ uart3: serial@11005000 {
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
clock-names = "baud", "bus";
+ reg-io-width = <4>;
+ reg-shift = <2>;
status = "disabled";
};
