From: Sudeep Holla <sudeep.holla@xxxxxxx>
The ARM MHU's reference manual states following:
"The MHU drives the signal using a 32-bit register, with all 32 bits
logically ORed together. The MHU provides a set of registers to enable
software to set, clear, and check the status of each of the bits of this
register independently. The use of 32 bits for each interrupt line
enables software to provide more information about the source of the
interrupt. For example, each bit of the register can be associated with
a type of event that can contribute to raising the interrupt."
This patch thus extends the MHU controller's DT binding to add support
for doorbell mode.
Though the same MHU hardware controller is used in the two modes, A new
compatible string is added here to represent the combination of the MHU
hardware and the firmware sitting on the other side (which expects each
bit to represent a different signal now).
Signed-off-by: Sudeep Holla <sudeep.holla@xxxxxxx>
Co-developed-by: Viresh Kumar <viresh.kumar@xxxxxxxxxx>
Signed-off-by: Viresh Kumar <viresh.kumar@xxxxxxxxxx>
---
V2:
- New compatible string and minor reformatting.
- Not sending as RFC anymore.
.../devicetree/bindings/mailbox/arm-mhu.txt | 44 +++++++++++++++++--
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
index 4971f03f0b33..1adc441a2c63 100644
--- a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
+++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
@@ -10,21 +10,41 @@ STAT register and the remote clears it after having read the data.
The last channel is specified to be a 'Secure' resource, hence can't be
used by Linux running NS.
+Doorbell mode: The MHU drives the interrupt signal using a 32-bit
+register, with all 32-bits logically ORed together. It provides a set of
+registers to enable software to set, clear and check the status of each
+of the bits of this register independently. The use of 32 bits per
+interrupt line enables software to provide more information about the
+source of the interrupt. For example, each bit of the register can be
+associated with a type of event that can contribute to raising the
+interrupt. Each of the 32-bits can be used as "doorbell" to alert the
+remote processor.
+
Mailbox Device Node:
====================
Required properties:
--------------------
-- compatible: Shall be "arm,mhu" & "arm,primecell"
+- compatible: Shall be "arm,mhu" (in data transfer mode) or
+ "arm,mhu-doorbell" (in doorbell mode) and
+ "arm,primecell".
- reg: Contains the mailbox register address range (base
address and length)
-- #mbox-cells Shall be 1 - the index of the channel needed.
+- #mbox-cells Shall be 1 - the index of the channel needed,
+ when used in data transfer mode.
+ Shall be 2 - the index of the channel needed, and
+ the index of the doorbell bit within the
+ channel, when used in doorbell mode.
- interrupts: Contains the interrupt information corresponding to
- each of the 3 links of MHU.
+ each of the 3 physical channels of MHU namely low
+ priority non-secure, high priority non-secure and
+ secure channels.
Example:
--------
+1. In data transfer mode
+
mhu: mailbox@2b1f0000 {
#mbox-cells = <1>;
compatible = "arm,mhu", "arm,primecell";
@@ -41,3 +61,21 @@ used by Linux running NS.
reg = <0 0x2e000000 0x4000>;
mboxes = <&mhu 1>; /* HP-NonSecure */
};
+
+2. In doorbell mode
+
+ mhu: mailbox@2b1f0000 {
+ #mbox-cells = <2>;
+ compatible = "arm,mhu-doorbell", "arm,primecell";
+ reg = <0 0x2b1f0000 0x1000>;
+ interrupts = <0 36 4>, /* LP-NonSecure */
+ <0 35 4>; /* HP-NonSecure */
+ clocks = <&clock 0 2 1>;
+ clock-names = "apb_pclk";
+ };
+
+ mhu_client: scb@2e000000 {
+ compatible = "arm,scpi";
+ reg = <0 0x2e000000 0x200>;
+ mboxes = <&mhu 1 4>; /* HP-NonSecure 5th doorbell bit */
+ };
--
2.25.0.rc1.19.g042ed3e048af
