Hi Russell, On Thu, 12 Jun 2014 03:15:03 -0700 Jisheng Zhang <jszhang@xxxxxxxxxxx> wrote: > Hi Russell, > > On Thu, 12 Jun 2014 02:44:23 -0700 > Russell King - ARM Linux <linux@xxxxxxxxxxxxxxxx> wrote: > > > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote: > > > For all BG2Q SoCs, 2 cycles is the best/correct value > > > > It would be a good idea to set all these parameters if you need to set > > them at all - in other words, setting arm,dirty-latency as well, as > > that's all part of the timing specification. > > > > Thanks for reviewing this patch. I will check with SoC people to find the > correct dirty-latency value. The BG2Q L2 cache controller is PL310, so no "dirty-latency" Thanks, Jisheng -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
