Re: [PATCH 13/14] arm64: dts: renesas: Add Renesas R8A779A0 SoC support

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Hi Shimoda-san,

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> Add initial support for the Renesas R8A77990 (R-Car V3U) support.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi

> +       soc: soc {

> +
> +               sysc: system-controller@e6180000 {
> +                       compatible = "renesas,r8a779a0-sysc";
> +                       reg = <0 0xe6180000 0 0x3078>;

Length 0x4000?

> +                       #power-domain-cells = <1>;
> +               };
> +
> +               scif0: serial@e6e60000 {
> +                       compatible = "renesas,scif-r8a779a0",
> +                                    "renesas,rcar-gen3-scif", "renesas,scif";
> +                       reg = <0 0xe6e60000 0 64>;
> +                       interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD 702>,
> +                                <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
> +                                <&scif_clk>;
> +                       clock-names = "fck", "brg_int", "scif_clk";
> +                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

Missing resets property.

> +                       status = "disabled";
> +               };
> +
> +               gic: interrupt-controller@f1000000 {
> +                       compatible = "arm,gic-v3";
> +                       #interrupt-cells = <3>;
> +                       #address-cells = <0>;
> +                       interrupt-controller;
> +                       reg = <0x0 0xf1000000 0 0x20000>,
> +                             <0x0 0xf1060000 0 0x110000>;
> +                       interrupts = <GIC_PPI 9
> +                                     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;

"GIC_CPU_MASK_SIMPLE(1)", as currently only one CPU core is used.

> +                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> +               };
> +
> +               prr: chipid@fff00044 {
> +                       compatible = "renesas,prr";
> +                       reg = <0 0xfff00044 0 4>;
> +               };
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

"GIC_CPU_MASK_SIMPLE(1)" for all 4 interrupts (and in the future "8",
not "2").

> +       };
> +};
> --
> 2.7.4
>



--
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds



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