On Thu, 2020-09-03 at 07:29 +0800, Suman Anna wrote:
> Hi Crystal,
>
> On 8/16/20 10:03 PM, Crystal Guo wrote:
> > add infracfg_rst node which is for MT8192 platform
> >
> > Signed-off-by: Crystal Guo <crystal.guo@xxxxxxxxxxxx>
>
> I understand you are posting these together for complete reference, but driver
> subsystem maintainers typically don't pick dts patches. In anycase, can you
> clarify if your registers are self-clearing registers?
>
> regards
> Suman
>
Hi Suman,
Thanks for your reply.
Our reset registers are not self-clearing, it needs to set the clear bit
to 1 to clear the related bit.
And should I separate this dts patch from the patch sets?
regards
Crystal
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 931e1ca17220..a0cb9904706b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -10,6 +10,7 @@
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > #include <dt-bindings/power/mt8192-power.h>
> > +#include <dt-bindings/reset/ti-syscon.h>
> >
> > / {
> > compatible = "mediatek,mt8192";
> > @@ -219,9 +220,17 @@
> > };
> >
> > infracfg: infracfg@10001000 {
> > - compatible = "mediatek,mt8192-infracfg", "syscon";
> > + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> > reg = <0 0x10001000 0 0x1000>;
> > #clock-cells = <1>;
> > +
> > + infracfg_rst: reset-controller {
> > + compatible = "mediatek,infra-reset", "ti,syscon-reset";
> > + #reset-cells = <1>;
> > + ti,reset-bits = <
> > + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: pcie */
> > + >;
> > + };
> > };
> >
> > pericfg: pericfg@10003000 {
> >
>
