Hi Morimoto-san,
On Tue, Sep 08, 2020 at 09:34:59AM +0900, Kuninori Morimoto wrote:
>
> From: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
>
> This patch adds VSP device nodes for R-Car M3-W+ (r8a77961) SoC.
> This patch was tested on R-Car M3-W+ Salvator-XS board.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/renesas/r8a77961.dtsi | 55 +++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
> index fe0db11b9cb9..423808b6cd58 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
> @@ -2012,6 +2012,17 @@ fcpf0: fcp@fe950000 {
> resets = <&cpg 615>;
> };
>
> + vspb: vsp@fe960000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfe960000 0 0x8000>;
> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 626>;
> + power-domains = <&sysc R8A77961_PD_A3VC>;
> + resets = <&cpg 626>;
> +
> + renesas,fcp = <&fcpvb0>;
> + };
> +
> fcpvb0: fcp@fe96f000 {
> compatible = "renesas,fcpv";
> reg = <0 0xfe96f000 0 0x200>;
> @@ -2020,6 +2031,17 @@ fcpvb0: fcp@fe96f000 {
> resets = <&cpg 607>;
> };
>
> + vspi0: vsp@fe9a0000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfe9a0000 0 0x8000>;
> + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 631>;
> + power-domains = <&sysc R8A77961_PD_A3VC>;
> + resets = <&cpg 631>;
> +
> + renesas,fcp = <&fcpvi0>;
> + };
> +
> fcpvi0: fcp@fe9af000 {
> compatible = "renesas,fcpv";
> reg = <0 0xfe9af000 0 0x200>;
> @@ -2029,6 +2051,17 @@ fcpvi0: fcp@fe9af000 {
> iommus = <&ipmmu_vc0 19>;
> };
>
> + vspd0: vsp@fea20000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfea20000 0 0x5000>;
> + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 623>;
> + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
> + resets = <&cpg 623>;
> +
> + renesas,fcp = <&fcpvd0>;
> + };
> +
> fcpvd0: fcp@fea27000 {
> compatible = "renesas,fcpv";
> reg = <0 0xfea27000 0 0x200>;
> @@ -2038,6 +2071,17 @@ fcpvd0: fcp@fea27000 {
> iommus = <&ipmmu_vi0 8>;
> };
>
> + vspd1: vsp@fea28000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfea28000 0 0x5000>;
> + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 622>;
> + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
> + resets = <&cpg 622>;
> +
> + renesas,fcp = <&fcpvd1>;
> + };
> +
> fcpvd1: fcp@fea2f000 {
> compatible = "renesas,fcpv";
> reg = <0 0xfea2f000 0 0x200>;
> @@ -2047,6 +2091,17 @@ fcpvd1: fcp@fea2f000 {
> iommus = <&ipmmu_vi0 9>;
> };
>
> + vspd2: vsp@fea30000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfea30000 0 0x5000>;
> + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 621>;
> + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
> + resets = <&cpg 621>;
> +
> + renesas,fcp = <&fcpvd2>;
> + };
> +
> fcpvd2: fcp@fea37000 {
> compatible = "renesas,fcpv";
> reg = <0 0xfea37000 0 0x200>;
--
Regards,
Laurent Pinchart
