[PATCH 07/14] dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions

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Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V3U (R8A779A0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
---
 include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 63 +++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a779a0-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
new file mode 100644
index 0000000..9ed14ea
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779A0 CPG Core Clocks */
+#define R8A779A0_CLK_Z0			0
+#define R8A779A0_CLK_ZX			1
+#define R8A779A0_CLK_Z1			2
+#define R8A779A0_CLK_ZR			3
+#define R8A779A0_CLK_ZS			4
+#define R8A779A0_CLK_ZT			5
+#define R8A779A0_CLK_ZTR		6
+#define R8A779A0_CLK_S1			7
+#define R8A779A0_CLK_S3			8
+#define R8A779A0_CLK_S1D1		9
+#define R8A779A0_CLK_S1D2		10
+#define R8A779A0_CLK_S1D4		11
+#define R8A779A0_CLK_S1D8		12
+#define R8A779A0_CLK_S1D12		13
+#define R8A779A0_CLK_S2D1		14
+#define R8A779A0_CLK_S2D2		15
+#define R8A779A0_CLK_S2D4		16
+#define R8A779A0_CLK_S3D1		17
+#define R8A779A0_CLK_S3D2		18
+#define R8A779A0_CLK_S3D4		19
+#define R8A779A0_CLK_LB			20
+#define R8A779A0_CLK_CP			21
+#define R8A779A0_CLK_CL			22
+#define R8A779A0_CLK_CL16MCK		23
+#define R8A779A0_CLK_ZB30		24
+#define R8A779A0_CLK_ZB30D2		25
+#define R8A779A0_CLK_ZB30D4		26
+#define R8A779A0_CLK_ZB31		27
+#define R8A779A0_CLK_ZB31D2		28
+#define R8A779A0_CLK_ZB31D4		29
+#define R8A779A0_CLK_SD0H		30
+#define R8A779A0_CLK_SD0		31
+#define R8A779A0_CLK_RPC		32
+#define R8A779A0_CLK_RPCD2		33
+#define R8A779A0_CLK_MSO		34
+#define R8A779A0_CLK_CANFD		35
+#define R8A779A0_CLK_CSI0		36
+#define R8A779A0_CLK_FRAY		37
+#define R8A779A0_CLK_POST		38
+#define R8A779A0_CLK_POST2		39
+#define R8A779A0_CLK_POST3		40
+#define R8A779A0_CLK_DSI		41
+#define R8A779A0_CLK_VIP		42
+#define R8A779A0_CLK_ADGH		43
+#define R8A779A0_CLK_CNNDSP		44
+#define R8A779A0_CLK_ICU		45
+#define R8A779A0_CLK_ICUD2		46
+#define R8A779A0_CLK_VCBUS		47
+#define R8A779A0_CLK_CBFUSA		48
+#define R8A779A0_CLK_RCLK		49
+#define R8A779A0_CLK_OSCCLK		50
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
-- 
2.7.4




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