On Sun, 2020-09-06 at 17:19 +0200, Fabien Parent wrote:
> This commit adds IOMMU binding documentation and larb port definitions
> for the MT8167 SoC.
>
> Signed-off-by: Fabien Parent <fparent@xxxxxxxxxxxx>
> Acked-by: Rob Herring <robh@xxxxxxxxxx>
> ---
>
> V3: Added mt8167-larb-port.h file for iommu port definitions
> V2: no change
>
> ---
> .../bindings/iommu/mediatek,iommu.txt | 1 +
> include/dt-bindings/memory/mt8167-larb-port.h | 49 +++++++++++++++++++
> 2 files changed, 50 insertions(+)
> create mode 100644 include/dt-bindings/memory/mt8167-larb-port.h
>
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> index c1ccd8582eb2..f7a348f48e0d 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> @@ -61,6 +61,7 @@ Required properties:
> "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW.
> "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
> generation one m4u HW.
> + "mediatek,mt8167-m4u" for mt8167 which uses generation two m4u HW.
> "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
> "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
> - reg : m4u register base and size.
Please also add this line in the iommu-cells property:
dt-bindings/memory/mt8167-larb-port.h for mt8167.
> diff --git a/include/dt-bindings/memory/mt8167-larb-port.h b/include/dt-bindings/memory/mt8167-larb-port.h
> new file mode 100644
> index 000000000000..4dd44d1037a7
> --- /dev/null
> +++ b/include/dt-bindings/memory/mt8167-larb-port.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2020 BayLibre, SAS
> + * Author: Fabien Parent <fparent@xxxxxxxxxxxx>
If I'm not wrong, the first version was created by:
Honghui Zhang <honghui.zhang@xxxxxxxxxxxx>
the original author should be kept.
> + */
> +#ifndef __DTS_IOMMU_PORT_MT8167_H
> +#define __DTS_IOMMU_PORT_MT8167_H
> +
> +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
> +
> +#define M4U_LARB0_ID 0
> +#define M4U_LARB1_ID 1
> +#define M4U_LARB2_ID 2
> +
> +/* larb0 */
> +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
> +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
> +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
> +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3)
> +#define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4)
> +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5)
> +#define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6)
> +#define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7)
> +
> +/* IMG larb1*/
> +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0)
> +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1)
> +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2)
> +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3)
> +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4)
> +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5)
> +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 6)
> +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7)
> +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8)
> +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9)
> +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10)
> +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11)
> +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12)
> +
> +/* VDEC larb2*/
> +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0)
> +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 1)
> +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2)
> +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3)
> +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4)
> +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5)
> +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6)
> +
> +#endif
