Hi Robert,
On Fri, Aug 28, 2020 at 02:13:30PM +0300, Robert Chiras (OSS) wrote:
> From: Robert Chiras <robert.chiras@xxxxxxx>
>
> The clock-drop-level is needed in order to add more blanking space needed
> by DSI panels when sending DSI commands. One level is the equivalent of
> phy_ref rate from the PLL rate. Since the PLL rate is targeted as highest
> possible, each level should not get the crtc_clock too low, compared to
> the actual clock.
Did you check whether this is only needed during panel prepare (when the
image sequence is being sent)? I wonder if this is an artifact of the
driver sending pixel data too early - and if it's not whether we have
something else wrong so that we need to have a longer blanking period
with some panels?
Cheers,
-- Guido
>
> Example for a clock of 132M, with "clock-drop-level = <1>" in dts file
> will result in a crtc_clock of 129M, using the following logic:
> - video_pll rate to provide both phy_ref rate of 24M and pixel-clock
> of 132M is 1056M (divisor /43 for phy_ref and /8 for pixel-clock)
> - from this rate, we subtract the equivalent of phy_ref (24M) but
> keep the same divisor. This way, the video_pll rate will be 1056 - 24
> = 1032M.
> - new pixel-clock will be: 1032 / 8 = 129M
>
> For a "clock-drop-level = <2>", new pixel-clock will be:
> (1056 - (24 * 2)) / 8 = 1008 / 8 = 126M
>
> Signed-off-by: Robert Chiras <robert.chiras@xxxxxxx>
> ---
> drivers/gpu/drm/bridge/nwl-dsi.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
> index 1228466..ac4aa0a 100644
> --- a/drivers/gpu/drm/bridge/nwl-dsi.c
> +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
> @@ -142,6 +142,7 @@ struct nwl_dsi {
>
> struct nwl_dsi_transfer *xfer;
> struct list_head valid_modes;
> + u32 clk_drop_lvl;
> };
>
> static const struct regmap_config nwl_dsi_regmap_config = {
> @@ -842,13 +843,14 @@ static unsigned long nwl_dsi_get_lcm(unsigned long a, unsigned long b)
>
> return ((unsigned long long)a * b) / gcf;
> }
> -
> /*
> * This function tries to adjust the crtc_clock for a DSI device in such a way
> * that the video pll will be able to satisfy both Display Controller pixel
> * clock (feeding out DPI interface) and our input phy_ref clock.
> + * Also, the DC pixel clock must be lower than the actual clock in order to
> + * have enough blanking space to send DSI commands, if the device is a panel.
> */
> -static void nwl_dsi_setup_pll_config(struct mode_config *config)
> +static void nwl_dsi_setup_pll_config(struct mode_config *config, u32 lvl)
> {
> unsigned long pll_rate;
> int div;
> @@ -908,7 +910,6 @@ static void nwl_dsi_setup_pll_config(struct mode_config *config)
> }
> }
>
> -
> /*
> * This function will try the required phy speed for current mode
> * If the phy speed can be achieved, the phy will save the speed
> @@ -1103,7 +1104,7 @@ nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge,
>
> pll_rate = config->pll_rates[config->phy_rate_idx];
> if (dsi->pll_clk && !pll_rate)
> - nwl_dsi_setup_pll_config(config);
> + nwl_dsi_setup_pll_config(config, dsi->clk_drop_lvl);
>
> return MODE_OK;
> }
> @@ -1248,6 +1249,7 @@ static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = {
> static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
> {
> struct platform_device *pdev = to_platform_device(dsi->dev);
> + struct device_node *np = dsi->dev->of_node;
> struct clk *clk;
> void __iomem *base;
> int ret;
> @@ -1364,6 +1366,8 @@ static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
> return PTR_ERR(dsi->rst_dpi);
> }
>
> + of_property_read_u32(np, "fsl,clock-drop-level", &dsi->clk_drop_lvl);
> +
> INIT_LIST_HEAD(&dsi->valid_modes);
>
> return 0;
> --
> 2.7.4
>
