The UART12 node has been mistakenly mentioned as UART2. Let's fix that for both SM8250 SoC and MTP board and also add pinctrl definition for it. Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 ++++++++++- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 6894f8490dae..6e2f7ae1d621 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -17,7 +17,7 @@ compatible = "qcom,sm8250-mtp"; aliases { - serial0 = &uart2; + serial0 = &uart12; }; chosen { @@ -371,7 +371,7 @@ gpio-reserved-ranges = <28 4>, <40 4>; }; -&uart2 { +&uart12 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 377172e8967b..e7d139e1a6ce 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -935,11 +935,13 @@ status = "disabled"; }; - uart2: serial@a90000 { + uart12: serial@a90000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00a90000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart12_default>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -1880,6 +1882,13 @@ bias-disable; }; }; + + qup_uart12_default: qup-uart12-default { + mux { + pins = "gpio34", "gpio35"; + function = "qup12"; + }; + }; }; adsp: remoteproc@17300000 { -- 2.17.1