Hi Prabhakar,
On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote:
> This patch enables CAN0 interface exposed through connector J20 on the
> carrier board.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Reviewed-by: Chris Paterson <Chris.Paterson2@xxxxxxxxxxx>
According to my schematics, the CAN port on J20 has its signals named
CAN0_[RT]XD on the carrier board, but connected to CAN1[RT]X (GP4_[67])
on the SoM.
Or am I looking at the wrong file?
> --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
> +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
> @@ -198,6 +198,13 @@
> };
> };
>
> +&can0 {
can1
> + pinctrl-0 = <&can0_pins>;
can1_pins
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> &cmt0 {
> status = "okay";
> };
> @@ -287,6 +303,11 @@
> function = "tpu0";
> };
>
> + can0_pins: can0 {
> + groups = "can0_data_d";
can1_data_b
> + function = "can0";
> + };
> +
> i2c2_pins: i2c2 {
> groups = "i2c2_b";
> function = "i2c2";
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
