> + priv->clk = devm_clk_get_optional(&phydev->mdio.dev, "sw_gphy"); > + if (IS_ERR(priv->clk)) > + return PTR_ERR(priv->clk); > + > + /* To get there, the mdiobus registration logic already enabled our > + * clock otherwise we would not have probed this device since we would > + * not be able to read its ID. To avoid artificially bumping up the > + * clock reference count, only do the clock enable from a phy_remove -> > + * phy_probe path (driver unbind, then rebind). > + */ > + if (!__clk_is_enabled(priv->clk)) > + ret = clk_prepare_enable(priv->clk); This i don't get. The clock subsystem does reference counting. So what i would expect to happen is that during scanning of the bus, phylib enables the clock and keeps it enabled until after probe. To keep things balanced, phylib would disable the clock after probe. If the driver wants the clock enabled all the time, it can enable it in the probe method. The common clock framework will then have two reference counts for the clock, so that when the probe exists, and phylib disables the clock, the CCF keeps the clock ticking. The PHY driver can then disable the clock in .remove. There are some PHYs which will enumerate with the clock disabled. They only need it ticking for packet transfer. Such PHY drivers can enable the clock only when needed in order to save some power when the interface is administratively down. Andrew
