Add the devicetree properties to enable instruction and data prefetch
on exynos4210 and exynos4412 which use the L2C-310 cache. No other
Exynos chip appears to be using this L2 cache hardware.
This follows the default bits being set in the l2c_aux_val register
for the Exynos platform, which can now be cleared as a result.
Signed-off-by: Guillaume Tucker <guillaume.tucker@xxxxxxxxxxxxx>
---
Notes:
v2: split patch to include devicetree changes only
arch/arm/boot/dts/exynos4210.dtsi | 2 ++
arch/arm/boot/dts/exynos4412.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index b4466232f0c1..7e0d253b26ef 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -102,6 +102,8 @@
reg = <0x10502000 0x1000>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
arm,tag-latency = <2 2 1>;
arm,data-latency = <2 2 1>;
};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 48868947373e..37efa247bf4d 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -218,6 +218,8 @@
reg = <0x10502000 0x1000>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
arm,tag-latency = <2 2 1>;
arm,data-latency = <3 2 1>;
arm,double-linefill = <1>;
--
2.20.1
