This is the first driver for the MStar/SigmaStar chips.
All of the chips so far have two instances of this
controller.
One instance controls what are called "IRQ" interrupts
by the vendor code I have seen.
The other instance controls what are called "FIQ" interrupts
by the vendor code. Presumably because they can be FIQ
interrupts. Right now the FIQ bypass is disabled in the
GIC so they operate just the same as the IRQ interrupts.
The register layouts are the same for both. The FIQ one
needs to have the status bit cleared on EOI.
RFC because this is my first interrupt controller driver
and I expect to have made a bunch of mistakes.
Daniel Palmer (3):
dt: bindings: interrupt-controller: Add binding description for
msc313-intc
ARM: mstar: msc313-intc interrupt controller driver
ARM: mstar: Add interrupt controller to base dtsi
.../mstar,msc313-intc.yaml | 79 +++++++
MAINTAINERS | 2 +
arch/arm/boot/dts/mstar-v7.dtsi | 20 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-msc313-intc.c | 222 ++++++++++++++++++
5 files changed, 324 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml
create mode 100644 drivers/irqchip/irq-msc313-intc.c
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2.27.0
