The patchset fixes a problem with TDMOUT sclk inverter found on the g12a and following SoCs. On the the axg, a single bit was enough to drive the inverter. On the g12a a bit was added to, somehow, change how the clock is sampled. For the inverter to behave as intended, the new bit should be the inverse of the inverter bit at all time. Quite a lot of lines for a single bit ... Jerome Brunet (3): clk: meson: add sclk-ws driver clk: meson: axg-audio: separate axg and g12a regmap tables clk: meson: axg-audio: fix g12a tdmout sclk inverter drivers/clk/meson/axg-audio.c | 214 +++++++++++++++++++++++++++++----- drivers/clk/meson/clk-phase.c | 56 +++++++++ drivers/clk/meson/clk-phase.h | 6 + 3 files changed, 246 insertions(+), 30 deletions(-) -- 2.25.4
