On Wed, 2020-07-29 at 15:45 +0800, Matthias Brugger wrote:
>
> On 29/07/2020 09:39, Crystal Guo wrote:
> > add infracfg_rst node which is for MT8192 platform
> >
> > Signed-off-by: Crystal Guo <crystal.guo@xxxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 +++++++++-
> > 1 file changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index b16dbbd..adc6239 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -217,9 +217,17 @@
> > };
> >
> > infracfg: infracfg@10001000 {
> > - compatible = "mediatek,mt8192-infracfg", "syscon";
> > + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> > reg = <0 0x10001000 0 0x1000>;
> > #clock-cells = <1>;
> > +
> > + infracfg_rst: reset-controller {
> > + compatible = "ti,syscon-reset";
> > + #reset-cells = <1>;
> > + ti,reset-bits = <
> > + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: pcie */
>
> You have Texas Instruments hardware inside infracfg? Are you sure?
>
TI reset-controller driver is a common driver, MTK SOC has the similar
control flow, thus can reuse it.
> > + >;
> > + };
> > };
> >
> > pericfg: pericfg@10003000 {
> >
