On Thu, Jul 23, 2020 at 10:38 PM Rob Herring <robh@xxxxxxxxxx> wrote: > > On Thu, Jul 23, 2020 at 07:54:09PM +0530, Anup Patel wrote: > > We add DT bindings documentation for CLINT device. > > > > Signed-off-by: Anup Patel <anup.patel@xxxxxxx> > > Reviewed-by: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx> > > Tested-by: Emil Renner Berhing <kernel@xxxxxxxx> > > --- > > .../bindings/timer/sifive,clint.yaml | 58 +++++++++++++++++++ > > 1 file changed, 58 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml > > > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > new file mode 100644 > > index 000000000000..8ad115611860 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > @@ -0,0 +1,58 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: SiFive Core Local Interruptor > > + > > +maintainers: > > + - Palmer Dabbelt <palmer@xxxxxxxxxxx> > > + - Anup Patel <anup.patel@xxxxxxx> > > + > > +description: > > + SiFive (and other RISC-V) SOCs include an implementation of the SiFive > > + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor > > + interrupts. It directly connects to the timer and inter-processor interrupt > > + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local > > + interrupt controller is the parent interrupt controller for CLINT device. > > + The clock frequency of CLINT is specified via "timebase-frequency" DT > > + property of "/cpus" DT node. The "timebase-frequency" DT property is > > + described in Documentation/devicetree/bindings/riscv/cpus.yaml > > + > > +properties: > > + compatible: > > + items: > > + - const: sifive,clint0 > > + - const: sifive,fu540-c000-clint > > Wrong order. Most specific goes first. Okay, will update. > > > + > > + description: > > + Should be "sifive,<chip>-clint" and "sifive,clint<version>". > > + Supported compatible strings are - > > + "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated > > + onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive > > + CLINT v0 IP block with no chip integration tweaks. > > + Please refer to sifive-blocks-ip-versioning.txt for details > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts-extended: > > + minItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts-extended > > Add: > > additionalProperties: false Okay, will add. > > > + > > +examples: > > + - | > > + clint@2000000 { > > timer@... Okay, will rename. > > > + compatible = "sifive,clint0", "sifive,fu540-c000-clint"; > > + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 > > + &cpu2intc 3 &cpu2intc 7 > > + &cpu3intc 3 &cpu3intc 7 > > + &cpu4intc 3 &cpu4intc 7>; > > + reg = <0x2000000 0x4000000>; > > 64MB of register space? Doesn't matter much for 64-bit, but would waste > lots of virtual space (low mem) on 32-bit. This is a typo. The register space size is 64KB not 64MB. I will update. > > > + }; > > +... > > -- > > 2.25.1 > > Regards, Anup
