On Tue, Jul 21, 2020 at 4:32 PM Daniel Lezcano
<daniel.lezcano@xxxxxxxxxx> wrote:
>
> On 17/07/2020 09:50, Anup Patel wrote:
> > We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
> > RISC-V NoMMU kernel).
> >
> > The CLINT MMIO device provides three things:
> > 1. 64bit free running counter register
> > 2. 64bit per-CPU time compare registers
> > 3. 32bit per-CPU inter-processor interrupt registers
> >
> > Unlike other timer devices, CLINT provides IPI registers along with
> > timer registers. To use CLINT IPI registers, the CLINT timer driver
> > provides IPI related callbacks to arch/riscv.
> >
> > Signed-off-by: Anup Patel <anup.patel@xxxxxxx>
> > Tested-by: Emil Renner Berhing <kernel@xxxxxxxx>
> > ---
> > drivers/clocksource/Kconfig | 9 ++
> > drivers/clocksource/Makefile | 1 +
> > drivers/clocksource/timer-clint.c | 231 ++++++++++++++++++++++++++++++
> > include/linux/cpuhotplug.h | 1 +
> > 4 files changed, 242 insertions(+)
> > create mode 100644 drivers/clocksource/timer-clint.c
> >
> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > index 91418381fcd4..e1ce0d510a03 100644
> > --- a/drivers/clocksource/Kconfig
> > +++ b/drivers/clocksource/Kconfig
> > @@ -658,6 +658,15 @@ config RISCV_TIMER
> > is accessed via both the SBI and the rdcycle instruction. This is
> > required for all RISC-V systems.
> >
> > +config CLINT_TIMER
> > + bool "Timer for the RISC-V platform"
> > + depends on GENERIC_SCHED_CLOCK && RISCV_M_MODE
> > + select TIMER_PROBE
> > + select TIMER_OF
> > + help
> > + This option enables the CLINT timer for RISC-V systems. The CLINT
> > + driver is usually used for NoMMU RISC-V systems.
>
> V3 has a comment about fixing the Kconfig option.
I have removed "default y" from the Kconfig option as-per your suggestions.
I looked at other Timer Kconfig options. Most of them have menuconfig name.
Also, we can certainly have different timer MMIO timer drivers in future. Do
you still insist on making this kconfig option totally silent ??
>
> [ ... ]
>
> > +{
> > + bool *registered = per_cpu_ptr(&clint_clock_event_registered, cpu);
> > + struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
> > +
> > + if (!(*registered)) {
> > + ce->cpumask = cpumask_of(cpu);
> > + clockevents_config_and_register(ce, clint_timer_freq, 200,
> > + ULONG_MAX);
> > + *registered = true;
> > + }
>
>
> I was unsure about the clockevents_config_and_register() multiple calls
> when doing the comment. It seems like it is fine to call it several
> times and that is done in several places like riscv or arch_arm_timer.
>
> It is probably safe to drop the 'registered' code here, sorry for the
> confusion.
Okay, will revert these changes.
>
> > + enable_percpu_irq(clint_timer_irq,
> > + irq_get_trigger_type(clint_timer_irq));
> > + return 0;
> > +}
> > +
>
> [ ... ]
>
>
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Regards,
Anup
