Initial support for the MStar/Sigmastar Armv7 based IP camera and dashcam SoCs. These chips are interesting in that they contain a Cortex-A7, peripherals and system memory in a single tiny QFN package that can be hand soldered allowing almost anyone to embed Linux in their projects. Signed-off-by: Daniel Palmer <daniel@xxxxxxxx> --- MAINTAINERS | 1 + arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-mstar/Kconfig | 26 ++++++++++++ arch/arm/mach-mstar/Makefile | 1 + arch/arm/mach-mstar/mstarv7.c | 80 +++++++++++++++++++++++++++++++++++ 6 files changed, 111 insertions(+) create mode 100644 arch/arm/mach-mstar/Kconfig create mode 100644 arch/arm/mach-mstar/Makefile create mode 100644 arch/arm/mach-mstar/mstarv7.c diff --git a/MAINTAINERS b/MAINTAINERS index 96110ee8a41c..e433847a7446 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2123,6 +2123,7 @@ L: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml +F: arch/arm/mach-mstar/ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky <mkpetch@xxxxxxxxxxxxxxxx> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2ac74904a3ce..d54c413ad937 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -668,6 +668,8 @@ source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-moxart/Kconfig" +source "arch/arm/mach-mstar/Kconfig" + source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-mvebu/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 59fde2d598d8..e7f4ca060c0f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -197,6 +197,7 @@ machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut machine-$(CONFIG_ARCH_MXS) += mxs +machine-$(CONFIG_ARCH_MSTARV7) += mstar machine-$(CONFIG_ARCH_NOMADIK) += nomadik machine-$(CONFIG_ARCH_NPCM) += npcm machine-$(CONFIG_ARCH_NSPIRE) += nspire diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig new file mode 100644 index 000000000000..52744fe32368 --- /dev/null +++ b/arch/arm/mach-mstar/Kconfig @@ -0,0 +1,26 @@ +menuconfig ARCH_MSTARV7 + bool "MStar/Sigmastar Armv7 SoC Support" + depends on ARCH_MULTI_V7 + select ARM_GIC + select ARM_HEAVY_MB + help + Support for newer MStar/Sigmastar SoC families that are + based on Armv7 cores like the Cortex A7 and share the same + basic hardware like the infinity and mercury series. + +if ARCH_MSTARV7 + +config MACH_INFINITY + bool "MStar/Sigmastar infinity SoC support" + default ARCH_MSTARV7 + help + Support for MStar/Sigmastar infinity IP camera SoCs. + +config MACH_MERCURY + bool "MStar/Sigmastar mercury SoC support" + default ARCH_MSTARV7 + help + Support for MStar/Sigmastar mercury dash camera SoCs. + Note that older Mercury2 SoCs are ARM9 based and not supported. + +endif diff --git a/arch/arm/mach-mstar/Makefile b/arch/arm/mach-mstar/Makefile new file mode 100644 index 000000000000..93b0391ede7e --- /dev/null +++ b/arch/arm/mach-mstar/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_MSTARV7) += mstarv7.o diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c new file mode 100644 index 000000000000..81a4cbcab206 --- /dev/null +++ b/arch/arm/mach-mstar/mstarv7.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree support for MStar/Sigmastar Armv7 SoCs + * + * Copyright (c) 2020 thingy.jp + * Author: Daniel Palmer <daniel@xxxxxxxxx> + */ + +#include <linux/init.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/io.h> + +/* + * In the u-boot code the area these registers are in is + * called "L3 bridge" and there are register descriptions + * for something in the same area called "AXI". + * + * It's not exactly known what this is but the vendor code + * for both u-boot and linux share calls to "flush the miu pipe". + * This seems to be to force pending CPU writes to memory so that + * the state is right before DMA capable devices try to read + * descriptors and data the CPU has prepared. Without doing this + * ethernet doesn't work reliably for example. + */ + +#define MSTARV7_L3BRIDGE_FLUSH 0x14 +#define MSTARV7_L3BRIDGE_STATUS 0x40 +#define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0) +#define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12) + +static void __iomem *l3bridge; + +static const char * const mstarv7_board_dt_compat[] __initconst = { + "mstar,infinity", + "mstar,infinity3", + "mstar,mercury5", + NULL, +}; + +/* + * This may need locking to deal with situations where an interrupt + * happens while we are in here and mb() gets called by the interrupt handler. + * + * The vendor code did have a spin lock but it doesn't seem to be needed and + * removing it hasn't caused any side effects so far. + * + * [writel|readl]_relaxed have to be used here because otherwise + * we'd end up right back in here. + */ +static void mstarv7_mb(void) +{ + /* toggle the flush miu pipe fire bit */ + writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH); + writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge + + MSTARV7_L3BRIDGE_FLUSH); + while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS) + & MSTARV7_L3BRIDGE_STATUS_DONE)) { + /* wait for flush to complete */ + } +} + +static void __init mstarv7_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge"); + l3bridge = of_iomap(np, 0); + if (l3bridge) + soc_mb = mstarv7_mb; + else + pr_warn("Failed to install memory barrier, DMA will be broken!\n"); +} + +DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)") + .dt_compat = mstarv7_board_dt_compat, + .init_machine = mstarv7_init, +MACHINE_END -- 2.27.0
