Silvaco provide a dual-role I3C master. Description is rather simple: it needs a register mapping, three clocks and an interrupt. Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> --- .../bindings/i3c/svc,i3c-master.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/svc,i3c-master.yaml diff --git a/Documentation/devicetree/bindings/i3c/svc,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/svc,i3c-master.yaml new file mode 100644 index 000000000000..11e670c6b76f --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/svc,i3c-master.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/svc,i3c-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silvaco I3C master + +maintainers: + - Conor Culhane <conor.culhane@xxxxxxxxxxx> + +properties: + compatible: + const: svc,i3c-master + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + description: | + There are three clocks: + pclk: System clock + fast_clk: Fast clock (for the bus) + slow_clk: Slow clock (for other events) + + items: + - const: pclk + - const: fast_clk + - const: slow_clk + + clocks: + minItems: 3 + maxItems: 3 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +examples: + - | + i3c-master@a0000000 { + compatible = "svc,i3c-master"; + clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>; + clock-names = "pclk", "fast_clk", "slow_clk"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + reg = <0x0 0xa0000000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; -- 2.20.1
