NXP imx8MPlus integrates 2 indentical dwc3 3.30b IP with additional wakeup
logic to support low power, this wakeup logic has a separated interrupt
which can generate events with suspend clock(32K); due to SoC integration
limitation, a few quriks required, instead of create new properties flags,
introduce platform data and pass it from glue layer to dwc3 core, those xhci
private data can further pass to xhci-plat.
Changes for v2:
- Drop the 2 patches for new property("snps,xhci-dis-64bit-support-quirk")
introduction, as suggested, imply by SoC compatible string, this is done
by introduce dwc3 core platform data and pass the xhci_plat_priv to
xhci-plat for those xhci quirks, so a new patch added:
[1/5] usb: dwc3: add platform data to dwc3 core device to pass data.
this patch is based on Peter's one patch which is also in review:
https://patchwork.kernel.org/patch/11640945/
- dts change, use the USB power function of TRL logic instead of a always-on
regulator to control vbus on/off.
- Some changes to address Peter's command on patch [2/5].
Li Jun (5):
usb: dwc3: add platform data to dwc3 core device to pass data
usb: dwc3: add imx8mp dwc3 glue layer driver
arm64: dtsi: imx8mp: add usb nodes
arm64: dts: imx8mp-evk: enable usb1 as host mode
dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
.../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 87 +++++
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 21 ++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 77 +++++
drivers/usb/dwc3/Kconfig | 10 +
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/core.h | 5 +
drivers/usb/dwc3/dwc3-imx8mp.c | 374 +++++++++++++++++++++
drivers/usb/dwc3/host.c | 9 +
8 files changed, 584 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
create mode 100644 drivers/usb/dwc3/dwc3-imx8mp.c
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2.7.4
