We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel <anup.patel@xxxxxxx>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx>
---
.../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt
new file mode 100644
index 000000000000..45b75347a7d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt
@@ -0,0 +1,34 @@
+SiFive Core Local Interruptor (CLINT)
+-------------------------------------
+
+SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core
+Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts.
+
+It directly connects to the timer and inter-processor interrupt lines of
+various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt
+controller is the parent interrupt controller for CLINT device.
+
+The clock frequency of CLINT is specified via "timebase-frequency" DT
+property of "/cpus" DT node. The "timebase-frequency" DT property is
+described in: Documentation/devicetree/bindings/riscv/cpus.yaml
+
+Required properties:
+- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific
+ string identifying the actual implementation can be added if implementation
+ specific worked arounds are needed.
+- reg : Should contain 1 register range (address and length).
+- interrupts-extended : Specifies which HARTs (or CPUs) are connected to
+ the CLINT. Each node pointed to should be a riscv,cpu-intc node, which
+ has a riscv node as parent.
+
+Example:
+
+ clint@2000000 {
+ compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint";
+ interrupts-extended = <
+ &cpu1-intc 3 &cpu1-intc 7
+ &cpu2-intc 3 &cpu2-intc 7
+ &cpu3-intc 3 &cpu3-intc 7
+ &cpu4-intc 3 &cpu4-intc 7>;
+ reg = <0x2000000 0x4000000>;
+ };
--
2.25.1
