Re: [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk

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Subject: Re: [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
From: Stephen Boyd <sboyd@xxxxxxxxxx>
Date: Fri, 19 Jun 2020 19:37:48 -0700
Cc: dinguyen@xxxxxxxxxx, devicetree@xxxxxxxxxxxxxxx, mturquette@xxxxxxxxxxxx, robh+dt@xxxxxxxxxx
In-reply-to: <20200616202417.14376-2-dinguyen@kernel.org>
User-agent: alot/0.9

Quoting Dinh Nguyen (2020-06-16 13:24:16)
> And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main
> clock that is feeding the NAND IP and correct it's parent to be the
> l4_mp_clk.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---

Applied to clk-next

References:
- [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK
  - From: Dinh Nguyen
- [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
  - From: Dinh Nguyen

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