On Tue, Jun 09, 2020 at 03:40:18PM +0800, Yifeng Zhao wrote: > Documentation support for Rockchip RK3xxx NAND flash controllers > > Signed-off-by: Yifeng Zhao <yifeng.zhao@xxxxxxxxxxxxxx> > --- > > Changes in v6: > - Fix some wrong define > - Modified the definition of compatible > > Changes in v5: > - Fix some wrong define > - Add boot-medium define > - Remove some compatible define > > Changes in v4: > - The compatible define with rkxx_nfc > - Add assigned-clocks > - Fix some wrong define > > Changes in v3: > - Change the title for the dt-bindings > > Changes in v2: None > > .../mtd/rockchip,nand-controller.yaml | 154 ++++++++++++++++++ > 1 file changed, 154 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml > > diff --git a/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml > new file mode 100644 > index 000000000000..f753fe8248aa > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml > @@ -0,0 +1,154 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip SoCs NAND FLASH Controller (NFC) > + > +allOf: > + - $ref: "nand-controller.yaml#" > + > +maintainers: > + - Heiko Stuebner <heiko@xxxxxxxxx> > + > +properties: > + compatible: > + oneOf: > + - const: rockchip,px30-nfc > + - const: rockchip,rk2928-nfc > + - const: rockchip,rv1108-nfc > + - items: > + - const: rockchip,rk3326-nfc > + - const: rockchip,px30-nfc > + - items: > + - const: rockchip,rk3036-nfc > + - const: rockchip,rk2928-nfc > + - items: > + - const: rockchip,rk3308-nfc > + - const: rockchip,rv1108-nfc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + items: > + - description: Bus Clock > + - description: Module Clock > + > + clock-names: > + minItems: 1 > + items: > + - const: ahb > + - const: nfc > + > + assigned-clocks: > + maxItems: 1 > + > + assigned-clock-rates: > + maxItems: 1 > + > + pinctrl-0: > + maxItems: 1 > + > + pinctrl-names: > + const: default > + > + power-domains: > + maxItems: 1 > + > +patternProperties: > + "^nand@[a-f0-9]$": > + type: object > + properties: > + reg: > + minimum: 0 > + maximum: 7 > + > + nand-ecc-mode: > + const: hw > + > + nand-ecc-step-size: > + const: 1024 > + > + nand-ecc-strength: > + enum: [16, 24, 40, 60, 70] > + description: This needs a '|' at the end if you want the below line breaks preserved. > + The ECC configurations that can be supported are as follows. > + - NFCv900(PX30 and RK3326) support ecc strength 16, 40, 60 and 70. > + - NFCv600(RK3066 and RK2928) support ecc strength 16, 24, 40 and 60. > + - NFCv622(RK3036 and RK3128) support ecc strength 16, 24, 40 and 60. > + - NFCv800(RK3308 and RV1108) support ecc strength 16. > + > + nand-bus-width: > + const: 8 > + > + rockchip,boot-blks: > + minimum: 2 > + default: 16 > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + The NFC driver need this information to select ECC > + algorithms supported by the BOOTROM. > + Only used in combination with 'nand-is-boot-medium'. > + > + rockchip,boot-ecc-strength: > + enum: [16, 24, 40, 60, 70] > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + If specified it indicates that a different BCH/ECC setting is > + supported by the BOOTROM. > + - NFCv900(PX30 and RK3326) support ecc strength 16 and 70. > + - NFCv600(RK3066 and RK2928) support ecc strength 16, 24, 40 and 60. > + - NFCv622(RK3036 and RK3128) support ecc strength 16, 24, 40 and 60. > + - NFCv800(RK3308 and RV1108) support ecc strength 16. > + Only used in combination with 'nand-is-boot-medium'. > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + > +examples: > + - | > + #include <dt-bindings/clock/rk3308-cru.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + nfc: nand-controller@ff4b0000 { > + compatible = "rockchip,rk3308-nfc", > + "rockchip,rv1108-nfc"; > + reg = <0x0 0xff4b0000 0x0 0x4000>; > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; > + clock-names = "ahb", "nfc"; > + assigned-clocks = <&clks SCLK_NANDC>; > + assigned-clock-rates = <150000000>; > + > + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 > + &flash_rdn &flash_rdy &flash_wrn>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + nand@0 { > + reg = <0>; > + label = "rk-nand"; > + nand-bus-width = <8>; > + nand-ecc-mode = "hw"; > + nand-ecc-step-size = <1024>; > + nand-ecc-strength = <16>; > + nand-is-boot-medium; > + rockchip,boot-blks = <8>; > + rockchip,boot-ecc-strength = <16>; > + }; > + }; > + > +... > -- > 2.17.1 > > >
