BCM6368 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@xxxxxxxxx> Acked-by: Florian Fainelli <f.fainelli@xxxxxxxxx> --- v7: no changes. v6: no changes. v5: no changes. v4: no changes. v3: add reset controller definitions header file. v2: no changes. arch/mips/boot/dts/brcm/bcm6368.dtsi | 6 ++++++ include/dt-bindings/reset/bcm6368-reset.h | 16 ++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 include/dt-bindings/reset/bcm6368-reset.h diff --git a/arch/mips/boot/dts/brcm/bcm6368.dtsi b/arch/mips/boot/dts/brcm/bcm6368.dtsi index 449c167dd892..52c19f40b9cc 100644 --- a/arch/mips/boot/dts/brcm/bcm6368.dtsi +++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi @@ -70,6 +70,12 @@ reboot: syscon-reboot@10000008 { mask = <0x1>; }; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + periph_intc: interrupt-controller@10000020 { compatible = "brcm,bcm6345-l1-intc"; reg = <0x10000020 0x10>, diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h new file mode 100644 index 000000000000..c81d8eb6d173 --- /dev/null +++ b/include/dt-bindings/reset/bcm6368-reset.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6368_H +#define __DT_BINDINGS_RESET_BCM6368_H + +#define BCM6368_RST_SPI 0 +#define BCM6368_RST_MPI 3 +#define BCM6368_RST_IPSEC 4 +#define BCM6368_RST_EPHY 6 +#define BCM6368_RST_SAR 7 +#define BCM6368_RST_SWITCH 10 +#define BCM6368_RST_USBD 11 +#define BCM6368_RST_USBH 12 +#define BCM6368_RST_PCM 13 + +#endif /* __DT_BINDINGS_RESET_BCM6368_H */ -- 2.27.0