This patchset enables basic support for RoseapplePi, relying exclusively on the existing infrastructure for the Actions Semi Sxx SoCs (thank you Andreas and Manni for making this possible). The SBC is powered by the Actions Semi S500 SoC and comes with 2GB RAM, uSD slot and optional eMMC storage. For more details, please check: http://roseapplepi.org/index.php/spec/ The upcoming patches will improve this initial support by adding the missing bits and pieces to the S500 clock management unit, which is a prerequisite for providing an S500 pinctrl and gpio driver, in order to eventually enable access to additional functionality like I2C and MMC. Thanks and regards, Cristian Ciocaltea Cristian Ciocaltea (4): arm: dts: owl-s500: Fix incorrect PPI interrupt specifiers dt-bindings: Add vendor prefix for RoseapplePi.org dt-bindings: arm: actions: Document RoseapplePi arm: dts: owl-s500: Add RoseapplePi .../devicetree/bindings/arm/actions.yaml | 1 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/owl-s500-roseapplepi.dts | 47 +++++++++++++++++++ arch/arm/boot/dts/owl-s500.dtsi | 6 +-- 5 files changed, 54 insertions(+), 3 deletions(-) create mode 100644 arch/arm/boot/dts/owl-s500-roseapplepi.dts -- 2.27.0
