Hi Andreas,
On Thu, 11 Jun 2020 at 22:45, Andreas Färber <afaerber@xxxxxxx> wrote:
> > + compatible = "thingyjp,breadbee-crust", "mstar,infinity";
> > +
> > + aliases {
> > + serial0 = &pm_uart;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +};
> > +
> > +&pm_uart {
> > + status = "okay";
>
> Might this be a more suited place for temporary clock-frequency? For
> lack of clk driver it would seem to depend on the board's bootloader
> pre-configuring it rather than being a default of the SoC.
For all of the chips so far their second stage bootloader always turns
on a PLL and
reconfigures the pm_uart clock to use a 172MHz tap from that PLL right
at the start
of the boot process before u-boot is started. The new u-boot SPL I'm
working on to replace
that loader follows that convention.
Once the clk parts are in it should be possible to pull out the fixed
frequency and
replace it with a proper handle to that PLL tap.
Basically it's not documented anywhere except the assembly but the
convention for
these chips is to use the 172MHz clock for the uart pretty soon after
power on so it
made sense to have it in one place.
Thanks,
Daniel
