On Fri, 2020-05-29 at 13:24 -0600, Rob Herring wrote: > On Thu, May 28, 2020 at 05:57:09PM +0800, EastL wrote: > > Document the devicetree bindings for MediaTek Command-Queue DMA controller > > which could be found on MT6779 SoC or other similar Mediatek SoCs. > > > > Signed-off-by: EastL <EastL.Lee@xxxxxxxxxxxx> > > Need a full name OK > . > > > --- > > .../devicetree/bindings/dma/mtk-cqdma.yaml | 100 +++++++++++++++++++++ > > 1 file changed, 100 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > > > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > new file mode 100644 > > index 0000000..045aa0c > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml > > @@ -0,0 +1,100 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > Dual license new bindings: > > (GPL-2.0-only OR BSD-2-Clause) OK > > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek Command-Queue DMA controller Device Tree Binding > > + > > +maintainers: > > + - EastL <EastL.Lee@xxxxxxxxxxxx> > > + > > +description: > > + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC > > + is dedicated to memory-to-memory transfer through queue based > > + descriptor management. > > + > > Need a $ref to dma-controller.yaml OK > > > +properties: > > + "#dma-cells": > > + minimum: 1 > > + # Should be enough > > + maximum: 255 > > + description: > > + Used to provide DMA controller specific information. > > + > > + compatible: > > + const: mediatek,cqdma > > Needs SoC specific compatible string(s). OK > > > + > > + reg: > > + minItems: 1 > > + maxItems: 255 > > You can have 255 register regions? No, I'll fix maxItems to 5 > > You need to define what each region is if more than 1. > > > + > > + interrupts: > > + minItems: 1 > > + maxItems: 255 > > 255 interrupts? the same, 5 interripts. > > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + const: cqdma > > + > > + dma-channel-mask: > > + description: > > + Bitmask of available DMA channels in ascending order that are > > + not reserved by firmware and are available to the > > + kernel. i.e. first channel corresponds to LSB. > > + The first item in the array is for channels 0-31, the second is for > > + channels 32-63, etc. > > + allOf: > > + - $ref: /schemas/types.yaml#/definitions/uint32-array > > + items: > > + minItems: 1 > > + # Should be enough > > + maxItems: 255 > > This already has a definition in dma-common.yaml. Don't copy-n-paste > it. Just add any constraints you have. Like what is the max number of > channels? OK, the max channel number is 5, I'll fix it on next version. > > > + > > + dma-channels: > > + $ref: /schemas/types.yaml#definitions/uint32 > > + description: > > + Number of DMA channels supported by the controller. > > + > > + dma-requests: > > + $ref: /schemas/types.yaml#definitions/uint32 > > + description: > > + Number of DMA request signals supported by the controller. > > Same comment on these 2. OK > > > + > > +required: > > + - "#dma-cells" > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + - dma-channel-mask > > + - dma-channels > > + - dma-requests > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/clock/mt6779-clk.h> > > + cqdma: dma-controller@10212000 { > > + compatible = "mediatek,cqdma"; > > + reg = <0 0x10212000 0 0x80>, > > + <0 0x10212080 0 0x80>, > > + <0 0x10212100 0 0x80>; > > Examples default to 1 cell each for address and size. OK > > > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>, > > + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>, > > + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; > > + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>; > > + clock-names = "cqdma"; > > + dma-channel-mask = <63>; > > + dma-channels = <3>; > > + dma-requests = <32>; > > + #dma-cells = <1>; > > + }; > > + > > +... > > -- > > 1.9.1
