BCM6328 SoCs have a reset controller for certain components.
Signed-off-by: Álvaro Fernández Rojas <noltari@xxxxxxxxx>
---
v2: no changes.
arch/mips/boot/dts/brcm/bcm6328.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/boot/dts/brcm/bcm6328.dtsi b/arch/mips/boot/dts/brcm/bcm6328.dtsi
index af860d06def6..590118cf5c12 100644
--- a/arch/mips/boot/dts/brcm/bcm6328.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi
@@ -57,6 +57,12 @@ clkctl: clock-controller@10000004 {
#clock-cells = <1>;
};
+ periph_rst: reset-controller@10000010 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x10000010 0x4>;
+ #reset-cells = <1>;
+ };
+
periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>,
--
2.26.2
