[PATCH 1/2] dt-bindings: watchdog: intel: Add YAML Schemas for Watchdog timer

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Add YAML schemas for the watchdog timer on Intel Lightning
Mountain SoC.

Signed-off-by: Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx>
---
 .../bindings/watchdog/intel,lgm-gptc-wdt.yaml      | 75 ++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/watchdog/intel,lgm-gptc-wdt.yaml

diff --git a/Documentation/devicetree/bindings/watchdog/intel,lgm-gptc-wdt.yaml b/Documentation/devicetree/bindings/watchdog/intel,lgm-gptc-wdt.yaml
new file mode 100644
index 0000000000000..83dc39a5090c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/intel,lgm-gptc-wdt.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/intel,lgm-gptc-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightning Mountain Watchdog timer.
+
+maintainers:
+  - Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx>
+
+description: |
+  Intel Lightning Mountain SoC has General Purpose Timer Counter(GPTC) which can
+  be configured as Clocksource, real time clock and Watchdog timer.
+  Each General Purpose Timer Counter has three timers. And total four General
+  Purpose Timer Counters are present on Lightning Mountain SoC which sums up
+  to 12 timers.
+  Lightning Mountain has four CPUs and each CPU is configured with one GPTC
+  timer as watchdog timer. Total four timers are configured as watchdog timers
+  on Lightning Mountain SoC.
+
+allOf:
+  - $ref: "watchdog.yaml#"
+
+properties:
+  compatible:
+    enum:
+      - intel,lgm-gptc-wdt
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Frequency clock
+      - description: Core clock
+
+  clock-names:
+    items:
+      - const: freq
+      - const: gptc
+
+  intel,wdt-rst-hndl:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: Watchdog timer registers handle
+
+  intel,timer-cfg:
+    description: Watchdog Timer id and CPU id
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32-array
+      - minItems: 2
+        maxItems: 4
+        items:
+          minimum: 0
+          maximum: 3
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - intel,wdt-rst-hndl
+  - intel,timer-cfg
+
+examples:
+  - |
+    watchdog@e2500000 {
+      compatible = "intel,lgm-gptc-wdt";
+      reg = <0xe2500000 0x10000>;
+      intel,wdt-rst-hndl = <&sysconf>;
+      clocks = <&cgu0 31>, <&cgu0 136>;
+      clock-names = "freq", "gptc";
+      timeout-sec = <30>;
+      intel,timer-cfg =  <1 0 2 1>;
+    };
-- 
2.11.0




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