On Fri, Jun 05, 2020 at 12:34:36PM +0100, Robin Murphy wrote: > On 2020-06-04 22:28, Florian Fainelli wrote: > > For the BCM2835 case which is deemed performance critical, we would like > > to continue using an interrupt handler which does not have the extra > > comparison on BCM2835_SPI_CS_INTR. > FWIW, if I'm reading the patch correctly, then with sensible codegen that > "overhead" should amount to a bit test on a live register plus a not-taken > conditional branch - according to the 1176 TRM that should add up to a > whopping 2 cycles. If that's really significant then I'd have to wonder > whether you want to be at the mercy of the whole generic IRQ stack at all, > and should perhaps consider using FIQ instead. Yes, and indeed the compiler does seem to manage that. It *is* non-zero overhead though.
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